| /dpdk/drivers/regex/mlx5/ |
| H A D | mlx5_regex_control.c | 214 log_desc = rte_log2_u32(cfg->nb_desc); in mlx5_regex_qp_setup()
235 log_desc = rte_log2_u32(qp->nb_desc / qp->nb_obj); in mlx5_regex_qp_setup()
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| /dpdk/drivers/net/thunderx/base/ |
| H A D | nicvf_plat.h | 34 #define nicvf_log2_u32(x) rte_log2_u32(x)
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| /dpdk/drivers/net/mlx4/ |
| H A D | mlx4_rxq.c | 210 .log_ind_tbl_size = rte_log2_u32(RTE_DIM(ind_tbl)), in mlx4_rss_attach()
334 uint8_t log2_range = rte_log2_u32(dev->data->nb_rx_queues); in mlx4_rss_init()
815 .elts_n = rte_log2_u32(desc), in mlx4_rx_queue_setup()
843 sges_n = rte_log2_u32((size / mb_len) + !!(size % mb_len)); in mlx4_rx_queue_setup()
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| H A D | mlx4.c | 532 uint32_t ports = rte_log2_u32(conf->ports.present + 1); in mlx4_arg_parse()
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| /dpdk/app/test/ |
| H A D | test_common.c | 223 compare = rte_log2_u32(0); in test_log2()
249 compare = rte_log2_u32((uint32_t)i); in test_log2()
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| /dpdk/drivers/net/ionic/ |
| H A D | ionic_dev.c | 350 .q_init.ring_size = rte_log2_u32(q->num_descs), in ionic_dev_cmd_adminq_init()
415 ring_size = rte_log2_u32(num_descs); in ionic_q_init()
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| H A D | ionic_lif.c | 1382 .ring_size = rte_log2_u32(q->num_descs), in ionic_lif_notifyq_init()
1488 .ring_size = rte_log2_u32(q->num_descs), in ionic_lif_txq_init()
1536 .ring_size = rte_log2_u32(q->num_descs), in ionic_lif_rxq_init()
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| /dpdk/drivers/common/mlx5/ |
| H A D | mlx5_common_devx.c | 132 attr->log_page_size = rte_log2_u32(page_size); in mlx5_devx_cq_create()
249 attr->wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE); in mlx5_devx_sq_create()
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| H A D | mlx5_devx_cmds.c | 358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); in mlx5_devx_cmd_mkey_create()
2193 rte_log2_u32(attr->num_of_send_wqbbs)); in mlx5_devx_cmd_create_qp()
2204 rte_log2_u32(attr->num_of_receive_wqes)); in mlx5_devx_cmd_create_qp()
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| /dpdk/drivers/vdpa/mlx5/ |
| H A D | mlx5_vdpa_event.c | 582 uint16_t log_desc_n = rte_log2_u32(desc_n); in mlx5_vdpa_event_qp_create()
598 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE); in mlx5_vdpa_event_qp_create()
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| /dpdk/drivers/common/cnxk/ |
| H A D | roc_platform.h | 93 #define plt_log2_u32 rte_log2_u32
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| H A D | cnxk_security.c | 349 sa->w0.s.ar_win = rte_log2_u32(replay_win_sz) - 5; in cnxk_ot_ipsec_inb_sa_fill()
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| /dpdk/drivers/net/nfp/ |
| H A D | nfp_rxtx.c | 593 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc)); in nfp_net_rx_queue_setup()
790 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc)); in nfp_net_tx_queue_setup()
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| /dpdk/drivers/compress/mlx5/ |
| H A D | mlx5_compress.c | 193 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops); in mlx5_compress_qp_setup()
344 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), in mlx5_compress_xform_create()
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| /dpdk/lib/eal/include/ |
| H A D | rte_common.h | 690 rte_log2_u32(uint32_t v) in rte_log2_u32() function
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| /dpdk/drivers/crypto/mlx5/ |
| H A D | mlx5_crypto.c | 597 uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors); in mlx5_crypto_queue_pair_setup()
623 log_wqbb_n = rte_log2_u32(RTE_BIT32(log_nb_desc) * in mlx5_crypto_queue_pair_setup()
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| /dpdk/drivers/event/cnxk/ |
| H A D | cnxk_eventdev_adptr.c | 195 rq->vwqe_max_sz_exp = rte_log2_u32(sz); in cnxk_sso_rx_adapter_vwqe_enable()
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| /dpdk/drivers/net/mlx5/ |
| H A D | mlx5_flow_hw.c | 748 rte_log2_u32(table_attr->nb_flows), in flow_hw_actions_translate()
1486 matcher_attr.rule.num_log = rte_log2_u32(nb_flows); in flow_hw_table_create()
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| H A D | mlx5_flow_dv.c | 6439 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); in flow_dv_mtr_pool_create()
12707 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL); in flow_dv_ct_pool_create()
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| /dpdk/drivers/net/bnxt/ |
| H A D | bnxt_ring.c | 401 rte_log2_u32(db->db_epoch_mask); in bnxt_set_db()
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| /dpdk/drivers/net/hns3/ |
| H A D | hns3_fdir.c | 449 rte_log2_u32(action->nb_queues)); in hns3_fd_ad_config()
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| /dpdk/drivers/net/mlx5/linux/ |
| H A D | mlx5_os.c | 1328 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); in mlx5_dev_spawn()
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