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Searched refs:reg_val (Results 1 – 25 of 50) sorted by relevance

12

/dpdk/drivers/net/octeontx_ep/
H A Dotx2_ep_vf.c13 volatile uint64_t reg_val = 0ull; in otx2_vf_setup_global_iq_reg() local
22 reg_val |= SDP_VF_R_IN_CTL_ESR; in otx2_vf_setup_global_iq_reg()
113 } while (reg_val != 0); in otx2_vf_setup_iq_regs()
196 uint64_t reg_val = 0ull; in otx2_vf_enable_iq() local
215 reg_val |= 0x1ull; in otx2_vf_enable_iq()
227 uint64_t reg_val = 0ull; in otx2_vf_enable_oq() local
230 reg_val |= 0x1ull; in otx2_vf_enable_oq()
259 uint64_t reg_val = 0ull; in otx2_vf_disable_iq() local
263 reg_val &= ~0x1ull; in otx2_vf_disable_iq()
274 reg_val &= ~0x1ull; in otx2_vf_disable_oq()
[all …]
H A Dotx_ep_vf.c27 reg_val |= OTX_EP_R_IN_CTL_ESR; in otx_ep_setup_global_iq_reg()
126 } while (reg_val != 0); in otx_ep_setup_iq_regs()
209 uint64_t reg_val = 0ull; in otx_ep_enable_iq() local
229 reg_val |= 0x1ull; in otx_ep_enable_iq()
241 uint64_t reg_val = 0ull; in otx_ep_enable_oq() local
260 reg_val |= 0x1ull; in otx_ep_enable_oq()
292 uint64_t reg_val = 0ull; in otx_ep_disable_iq() local
296 reg_val &= ~0x1ull; in otx_ep_disable_iq()
304 uint64_t reg_val = 0ull; in otx_ep_disable_oq() local
307 reg_val &= ~0x1ull; in otx_ep_disable_oq()
[all …]
/dpdk/drivers/net/liquidio/base/
H A Dlio_23xx_vf.c56 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST; in cn23xx_vf_reset_io_queues()
58 reg_val); in cn23xx_vf_reset_io_queues()
119 reg_val = in cn23xx_vf_setup_global_output_regs()
126 reg_val = in cn23xx_vf_setup_global_output_regs()
130 reg_val |= in cn23xx_vf_setup_global_output_regs()
303 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B; in cn23xx_vf_enable_io_queues()
306 reg_val); in cn23xx_vf_enable_io_queues()
314 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB; in cn23xx_vf_enable_io_queues()
317 reg_val); in cn23xx_vf_enable_io_queues()
328 reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB; in cn23xx_vf_enable_io_queues()
[all …]
/dpdk/drivers/common/cnxk/
H A Droc_cpt_debug.c141 uint64_t reg_val; in roc_cpt_afs_print() local
163 uint64_t reg_val; in cpt_lf_print() local
165 reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE); in cpt_lf_print()
166 plt_print(" CPT_LF_Q_BASE:\t%016lx", reg_val); in cpt_lf_print()
168 reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE); in cpt_lf_print()
169 plt_print(" CPT_LF_Q_SIZE:\t%016lx", reg_val); in cpt_lf_print()
177 reg_val = plt_read64(lf->rbase + CPT_LF_CTL); in cpt_lf_print()
178 plt_print(" CPT_LF_CTL:\t%016lx", reg_val); in cpt_lf_print()
183 reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT); in cpt_lf_print()
186 reg_val = plt_read64(lf->rbase + CPT_LF_INPROG); in cpt_lf_print()
[all …]
/dpdk/drivers/crypto/caam_jr/
H A Dcaam_jr_hw.c289 uint32_t reg_val = 0; in hw_job_ring_set_coalescing_param() local
301 reg_val |= (irq_coalescing_timer << JR_REG_JRCFG_LO_ICTT_SHIFT); in hw_job_ring_set_coalescing_param()
304 SET_JR_REG_LO(JRCFG, job_ring, reg_val); in hw_job_ring_set_coalescing_param()
314 uint32_t reg_val = 0; in hw_job_ring_enable_coalescing() local
324 reg_val = GET_JR_REG_LO(JRCFG, job_ring); in hw_job_ring_enable_coalescing()
327 reg_val |= JR_REG_JRCFG_LO_ICEN_EN; in hw_job_ring_enable_coalescing()
330 SET_JR_REG_LO(JRCFG, job_ring, reg_val); in hw_job_ring_enable_coalescing()
341 uint32_t reg_val = 0; in hw_job_ring_disable_coalescing() local
352 reg_val = GET_JR_REG_LO(JRCFG, job_ring); in hw_job_ring_disable_coalescing()
355 reg_val &= ~JR_REG_JRCFG_LO_ICEN_EN; in hw_job_ring_disable_coalescing()
[all …]
/dpdk/drivers/net/txgbe/
H A Dtxgbe_ipsec.c30 uint32_t reg_val = TXGBE_IPSRXIDX_WRITE | in txgbe_crypto_clear_ipsec_tables() local
42 uint32_t reg_val = TXGBE_IPSRXIDX_WRITE | in txgbe_crypto_clear_ipsec_tables() local
55 reg_val = TXGBE_IPSTXIDX_WRITE | index; in txgbe_crypto_clear_ipsec_tables()
75 uint32_t reg_val; in txgbe_crypto_add_sa() local
146 reg_val = TXGBE_IPSRXIDX_ENA | TXGBE_IPSRXIDX_WRITE | in txgbe_crypto_add_sa()
167 reg_val = TXGBE_IPSRXIDX_ENA | TXGBE_IPSRXIDX_WRITE | in txgbe_crypto_add_sa()
229 reg_val = TXGBE_IPSRXIDX_ENA | in txgbe_crypto_add_sa()
255 uint32_t reg_val; in txgbe_crypto_remove_sa() local
292 reg_val = TXGBE_IPSRXIDX_WRITE | in txgbe_crypto_remove_sa()
297 reg_val = TXGBE_IPSRXIDX_WRITE | in txgbe_crypto_remove_sa()
[all …]
/dpdk/drivers/raw/ntb/
H A Dntb_hw_intel.c49 uint8_t reg_val; in intel_ntb3_check_ppd() local
52 ret = rte_pci_read_config(hw->pci_dev, &reg_val, in intel_ntb3_check_ppd()
53 sizeof(reg_val), XEON_PPD_OFFSET); in intel_ntb3_check_ppd()
60 switch (reg_val & XEON_PPD_CONN_MASK) { in intel_ntb3_check_ppd()
72 if (reg_val & XEON_PPD_DEV_DSD) { in intel_ntb3_check_ppd()
81 if (reg_val & XEON_PPD_SPLIT_BAR_MASK) { in intel_ntb3_check_ppd()
92 uint32_t reg_val; in intel_ntb4_check_ppd() local
97 switch (reg_val & XEON_GEN4_PPD_CONN_MASK) { in intel_ntb4_check_ppd()
107 if (reg_val & XEON_GEN4_PPD_DEV_DSD) { in intel_ntb4_check_ppd()
278 uint16_t reg_val, reg_off; in intel_ntb_get_link_status() local
[all …]
/dpdk/drivers/net/qede/base/
H A Decore_init_fw_funcs.c690 u32 reg_val, i; in ecore_poll_on_qm_cmd_ready() local
692 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; in ecore_poll_on_qm_cmd_ready()
1500 u32 reg_val; in ecore_set_vxlan_enable() local
1509 reg_val = ecore_rd(p_hwfn, p_ptt, in ecore_set_vxlan_enable()
1534 u32 reg_val; in ecore_set_gre_enable() local
1546 reg_val = ecore_rd(p_hwfn, p_ptt, in ecore_set_gre_enable()
1589 u32 reg_val; in ecore_set_geneve_enable() local
1601 reg_val = ecore_rd(p_hwfn, p_ptt, in ecore_set_geneve_enable()
1634 u32 reg_val, cfg_mask; in ecore_set_vxlan_no_l2_enable() local
1644 reg_val |= cfg_mask; in ecore_set_vxlan_no_l2_enable()
[all …]
/dpdk/drivers/net/ixgbe/
H A Dixgbe_ipsec.c21 IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSRXIDX, reg_val, \
24 IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSRXIDX, reg_val, \
66 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_KEY | index; in ixgbe_crypto_clear_ipsec_tables()
74 reg_val = IPSRXIDX_WRITE | index; in ixgbe_crypto_clear_ipsec_tables()
95 uint32_t reg_val; in ixgbe_crypto_add_sa() local
167 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | in ixgbe_crypto_add_sa()
188 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | in ixgbe_crypto_add_sa()
203 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | in ixgbe_crypto_add_sa()
277 uint32_t reg_val; in ixgbe_crypto_remove_sa() local
331 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_IP | in ixgbe_crypto_remove_sa()
[all …]
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_x550.c2124 u32 reg_val; in ixgbe_setup_kr_speed_x550em() local
2604 u16 reg_slice, reg_val; in ixgbe_setup_mac_link_sfp_x550em() local
2632 reg_val); in ixgbe_setup_mac_link_sfp_x550em()
2648 u32 reg_val; in ixgbe_setup_sfi_x550a() local
2677 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_sfi_x550a()
2800 u32 reg_val; in ixgbe_setup_ixfi_x550em_x() local
2811 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_ixfi_x550em_x()
2826 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_ixfi_x550em_x()
2871 u32 reg_val; in ixgbe_setup_ixfi_x550em() local
3029 u32 reg_val; in ixgbe_setup_phy_loopback_x550em() local
[all …]
H A Dixgbe_82599.h33 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
34 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
H A Dixgbe_vf.c220 u32 reg_val; in ixgbe_stop_adapter_vf() local
241 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i)); in ixgbe_stop_adapter_vf()
242 reg_val &= ~IXGBE_RXDCTL_ENABLE; in ixgbe_stop_adapter_vf()
243 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); in ixgbe_stop_adapter_vf()
/dpdk/drivers/net/igc/
H A Digc_ethdev.h269 uint32_t reg_val = IGC_READ_REG(hw, reg); in igc_read_reg_check_set_bits() local
271 bits |= reg_val; in igc_read_reg_check_set_bits()
272 if (bits == reg_val) in igc_read_reg_check_set_bits()
281 uint32_t reg_val = IGC_READ_REG(hw, reg); in igc_read_reg_check_clear_bits() local
283 bits = reg_val & ~bits; in igc_read_reg_check_clear_bits()
284 if (bits == reg_val) in igc_read_reg_check_clear_bits()
H A Digc_ethdev.c1071 uint32_t reg_val; in eth_igc_start() local
1073 reg_val = IGC_READ_REG(hw, IGC_CTRL); in eth_igc_start()
1074 reg_val &= ~IGC_CTRL_SPEED_MASK; in eth_igc_start()
1077 IGC_WRITE_REG(hw, IGC_CTRL, reg_val); in eth_igc_start()
2437 uint32_t reg_val; in igc_vlan_hw_filter_enable() local
2441 reg_val = IGC_READ_REG(hw, IGC_RCTL); in igc_vlan_hw_filter_enable()
2442 reg_val &= ~IGC_RCTL_CFIEN; in igc_vlan_hw_filter_enable()
2443 reg_val |= IGC_RCTL_VFE; in igc_vlan_hw_filter_enable()
2444 IGC_WRITE_REG(hw, IGC_RCTL, reg_val); in igc_vlan_hw_filter_enable()
2553 uint32_t reg_val; in eth_igc_vlan_tpid_set() local
[all …]
/dpdk/drivers/net/axgbe/
H A Daxgbe_common.h1499 SET_BITS(reg_val, \
1502 AXGMAC_IOWRITE((_pdata), _reg, reg_val); \
1525 SET_BITS(reg_val, \
1550 SET_BITS(reg_val, \
1611 SET_BITS(reg_val, \
1614 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1632 SET_BITS(reg_val, \
1656 SET_BITS(reg_val, \
1690 SET_BITS(reg_val, \
1693 XP_IOWRITE((_pdata), (_reg), reg_val); \
[all …]
H A Daxgbe_dev.c128 unsigned int reg_val = 0; in axgbe_set_ext_mii_mode() local
134 reg_val |= (1 << port); in axgbe_set_ext_mii_mode()
265 unsigned int reg, reg_val; in axgbe_disable_tx_flow_control() local
278 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_disable_tx_flow_control()
280 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_disable_tx_flow_control()
291 unsigned int reg, reg_val; in axgbe_enable_tx_flow_control() local
314 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_enable_tx_flow_control()
321 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_enable_tx_flow_control()
1110 unsigned int i, j, reg, reg_val; in axgbe_config_queue_mapping() local
1134 reg_val = 0; in axgbe_config_queue_mapping()
[all …]
/dpdk/drivers/net/bnx2x/
H A Decore_init.h712 uint32_t reg_val; in ecore_set_mcp_parity() local
715 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
718 reg_val |= mcp_attn_ctl_regs[i].bits; in ecore_set_mcp_parity()
720 reg_val &= ~mcp_attn_ctl_regs[i].bits; in ecore_set_mcp_parity()
722 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
764 uint32_t reg_val, mcp_aeu_bits = in ecore_clear_blocks_parity() local
780 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
782 if (reg_val & reg_mask) in ecore_clear_blocks_parity()
785 reg_val & reg_mask); in ecore_clear_blocks_parity()
791 if (reg_val & mcp_aeu_bits) in ecore_clear_blocks_parity()
[all …]
/dpdk/drivers/net/hns3/
H A Dhns3_regs.c171 uint32_t *reg_val = data; in hns3_get_32_bit_regs() local
210 *reg_val++ = rte_le_to_cpu_32(*desc_data++); in hns3_get_32_bit_regs()
228 uint64_t *reg_val = data; in hns3_get_64_bit_regs() local
267 *reg_val++ = rte_le_to_cpu_64(*desc_data++); in hns3_get_64_bit_regs()
443 uint32_t *reg_val = (uint32_t *)*data; in hns3_get_dfx_regs() local
467 reg_val += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, reg_val); in hns3_get_dfx_regs()
470 *data = (void *)reg_val; in hns3_get_dfx_regs()
/dpdk/drivers/net/i40e/base/
H A Di40e_diag.c124 u16 reg_val; in i40e_diag_eeprom_test() local
127 ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val); in i40e_diag_eeprom_test()
129 ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) == in i40e_diag_eeprom_test()
H A Di40e_prototype.h84 u32 *reg_val);
86 u32 reg_val);
106 u32 reg_addr, u64 reg_val,
109 u32 reg_addr, u64 *reg_val,
579 u32 reg_addr, u32 *reg_val,
583 u32 reg_addr, u32 reg_val,
585 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
590 u32 reg_addr, u32 reg_val,
596 u32 reg_addr, u32 *reg_val,
H A Di40e_common.c1157 u32 reg_val; in i40e_pre_tx_queue_cfg() local
3584 if (reg_val == NULL) in i40e_aq_debug_read_register()
7065 *reg_val = 0; in i40e_led_get_reg()
7071 reg_val, NULL); in i40e_led_get_reg()
7089 u32 reg_val) in i40e_led_set_reg() argument
7099 reg_val, NULL); in i40e_led_set_reg()
7105 (u16)reg_val); in i40e_led_set_reg()
7126 u16 reg_val; in i40e_led_get_phy() local
7145 &reg_val); in i40e_led_get_phy()
7148 *val = reg_val; in i40e_led_get_phy()
[all …]
/dpdk/drivers/net/e1000/base/
H A De1000_i210.c828 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; in e1000_pll_workaround_i210() local
837 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; in e1000_pll_workaround_i210()
838 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); in e1000_pll_workaround_i210()
870 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); in e1000_pll_workaround_i210()
871 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
879 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); in e1000_pll_workaround_i210()
880 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
/dpdk/drivers/net/i40e/
H A Di40e_hash.c690 uint32_t reg, reg_val, mask; in i40e_hash_enable_pctype() local
700 reg_val = i40e_read_rx_ctl(hw, reg); in i40e_hash_enable_pctype()
703 if (reg_val & mask) in i40e_hash_enable_pctype()
706 reg_val |= mask; in i40e_hash_enable_pctype()
708 if (!(reg_val & mask)) in i40e_hash_enable_pctype()
711 reg_val &= ~mask; in i40e_hash_enable_pctype()
714 i40e_write_rx_ctl(hw, reg, reg_val); in i40e_hash_enable_pctype()
/dpdk/drivers/net/ngbe/
H A Dngbe_pf.c392 uint32_t reg_val; in ngbe_vf_set_multicast() local
417 reg_val = rd32(hw, NGBE_MCADDRTBL(mta_idx)); in ngbe_vf_set_multicast()
418 reg_val |= (1 << mta_shift); in ngbe_vf_set_multicast()
419 wr32(hw, NGBE_MCADDRTBL(mta_idx), reg_val); in ngbe_vf_set_multicast()
/dpdk/drivers/net/e1000/
H A Dem_rxtx.c1958 uint32_t reg_val; in eth_em_tx_init() local
1959 reg_val = E1000_READ_REG(hw, E1000_IOSFPC); in eth_em_tx_init()
1960 reg_val |= E1000_RCTL_RDMTS_HEX; in eth_em_tx_init()
1961 E1000_WRITE_REG(hw, E1000_IOSFPC, reg_val); in eth_em_tx_init()
1966 reg_val = E1000_READ_REG(hw, E1000_TARC(0)); in eth_em_tx_init()
1967 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; in eth_em_tx_init()
1968 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; in eth_em_tx_init()
1969 E1000_WRITE_REG(hw, E1000_TARC(0), reg_val); in eth_em_tx_init()

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