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Searched refs:reg_addr (Results 1 – 25 of 44) sorted by relevance

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/dpdk/drivers/crypto/nitrox/
H A Dnitrox_hal.c22 uint64_t reg_addr; in nps_pkt_input_ring_disable() local
25 reg_addr = NPS_PKT_IN_INSTR_CTLX(ring); in nps_pkt_input_ring_disable()
43 uint64_t reg_addr; in nps_pkt_solicited_port_disable() local
47 reg_addr = NPS_PKT_SLC_CTLX(port); in nps_pkt_solicited_port_disable()
68 uint64_t base_addr, reg_addr; in setup_nps_pkt_input_ring() local
128 uint64_t reg_addr; in setup_nps_pkt_solicit_output_port() local
134 reg_addr = NPS_PKT_SLC_CNTSX(port); in setup_nps_pkt_solicit_output_port()
152 reg_addr = NPS_PKT_SLC_CTLX(port); in setup_nps_pkt_solicit_output_port()
171 uint64_t reg_addr; in vf_get_vf_config_mode() local
176 reg_addr = AQMQ_QSZX(0); in vf_get_vf_config_mode()
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/dpdk/drivers/raw/ntb/
H A Dntb_hw_intel.c319 void *reg_addr; in intel_ntb_gen3_set_link() local
345 void *reg_addr; in intel_ntb_gen4_set_link() local
360 ppd0 = rte_read32(reg_addr); in intel_ntb_gen4_set_link()
362 rte_write32(ppd0, reg_addr); in intel_ntb_gen4_set_link()
365 ppd0 = rte_read32(reg_addr); in intel_ntb_gen4_set_link()
409 void *reg_addr; in intel_ntb_spad_read() local
428 spad_v = rte_read32(reg_addr); in intel_ntb_spad_read()
439 void *reg_addr; in intel_ntb_spad_write() local
459 rte_write32(spad_v, reg_addr); in intel_ntb_spad_write()
541 void *reg_addr; in intel_ntb_vector_bind() local
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/dpdk/drivers/baseband/fpga_5gnr_fec/
H A Dfpga_5gnr_fec.h299 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8() local
300 *((volatile uint8_t *)(reg_addr)) = payload; in fpga_reg_write_8()
307 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16() local
308 mmio_write_16(reg_addr, payload); in fpga_reg_write_16()
315 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32() local
316 mmio_write_32(reg_addr, payload); in fpga_reg_write_32()
323 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64() local
324 mmio_write_64(reg_addr, payload); in fpga_reg_write_64()
353 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32() local
364 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_16() local
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/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_yt.h73 s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
75 s32 ngbe_write_phy_reg_yt(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
78 u32 reg_addr, u32 device_type, u16 *phy_data);
80 u32 reg_addr, u32 device_type, u16 phy_data);
82 u32 reg_addr, u32 device_type, u16 *phy_data);
84 u32 reg_addr, u32 device_type, u16 phy_data);
H A Dngbe_phy.h55 s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
57 s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
59 s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
61 s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
H A Dngbe_phy_yt.c10 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_yt() argument
16 reg.addr = reg_addr; in ngbe_read_phy_reg_yt()
37 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_yt() argument
43 reg.addr = reg_addr; in ngbe_write_phy_reg_yt()
64 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_ext_yt() argument
66 ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr); in ngbe_read_phy_reg_ext_yt()
73 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_ext_yt() argument
75 ngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr); in ngbe_write_phy_reg_ext_yt()
82 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_sds_ext_yt() argument
85 ngbe_read_phy_reg_ext_yt(hw, reg_addr, device_type, phy_data); in ngbe_read_phy_reg_sds_ext_yt()
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H A Dngbe_phy.c250 s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, in ngbe_read_phy_reg_mdi() argument
256 command = NGBE_MDIOSCA_REG(reg_addr) | in ngbe_read_phy_reg_mdi()
291 s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr, in ngbe_read_phy_reg() argument
300 err = hw->phy.read_reg_unlocked(hw, reg_addr, device_type, in ngbe_read_phy_reg()
316 s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, in ngbe_write_phy_reg_mdi() argument
322 command = NGBE_MDIOSCA_REG(reg_addr) | in ngbe_write_phy_reg_mdi()
351 s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr, in ngbe_write_phy_reg() argument
360 err = hw->phy.write_reg_unlocked(hw, reg_addr, device_type, in ngbe_write_phy_reg()
H A Dngbe_phy_rtl.h76 s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
78 s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
H A Dngbe_phy_mvl.h89 s32 ngbe_read_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
91 s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
H A Dngbe_phy_rtl.c8 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_rtl() argument
14 reg.addr = reg_addr; in ngbe_read_phy_reg_rtl()
24 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_rtl() argument
30 reg.addr = reg_addr; in ngbe_write_phy_reg_rtl()
H A Dngbe_phy_mvl.c10 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_mvl() argument
16 reg.addr = reg_addr; in ngbe_read_phy_reg_mvl()
31 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_mvl() argument
37 reg.addr = reg_addr; in ngbe_write_phy_reg_mvl()
H A Dngbe_type.h346 s32 (*read_reg)(struct ngbe_hw *hw, u32 reg_addr,
348 s32 (*write_reg)(struct ngbe_hw *hw, u32 reg_addr,
350 s32 (*read_reg_unlocked)(struct ngbe_hw *hw, u32 reg_addr,
352 s32 (*write_reg_unlocked)(struct ngbe_hw *hw, u32 reg_addr,
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_x550.h35 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
37 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
43 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
45 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
75 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
77 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_phy.h135 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
137 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
139 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
141 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.c527 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg() argument
533 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, in ixgbe_read_phy_reg()
546 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_write_phy_reg() argument
552 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, in ixgbe_write_phy_reg()
1260 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_iosf_sb_reg() argument
1263 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, in ixgbe_read_iosf_sb_reg()
1276 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_iosf_sb_reg() argument
1279 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, in ixgbe_write_iosf_sb_reg()
H A Dixgbe_api.h40 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
42 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
180 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
182 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
/dpdk/drivers/net/cxgbe/base/
H A Dt4_regs.h7 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) argument
10 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) argument
17 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) argument
20 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) argument
26 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) argument
29 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) argument
33 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) argument
36 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) argument
H A Dadapter.h465 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg() argument
467 return CXGBE_READ_REG(adapter, reg_addr); in t4_read_reg()
478 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t4_write_reg() argument
480 CXGBE_WRITE_REG(adapter, reg_addr, val); in t4_write_reg()
491 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr, in t4_write_reg_relaxed() argument
494 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val); in t4_write_reg_relaxed()
504 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) in t4_read_reg64() argument
506 return CXGBE_READ_REG64(adapter, reg_addr); in t4_read_reg64()
517 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, in t4_write_reg64() argument
520 CXGBE_WRITE_REG64(adapter, reg_addr, val); in t4_write_reg64()
/dpdk/drivers/net/bnx2x/
H A Decore_init.h215 uint32_t reg_addr, reg_bit_map, vnic; in ecore_map_q_cos() local
236 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); in ecore_map_q_cos()
237 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
238 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
241 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); in ecore_map_q_cos()
242 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
243 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
248 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); in ecore_map_q_cos()
249 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
254 REG_WR(sc, reg_addr, reg_bit_map); in ecore_map_q_cos()
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_api_cmd.c442 u32 reg_addr, val; in api_cmd_hw_restart() local
446 reg_addr = HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(chain->chain_type); in api_cmd_hw_restart()
447 val = hinic_hwif_read_reg(hwif, reg_addr); in api_cmd_hw_restart()
452 hinic_hwif_write_reg(hwif, reg_addr, val); in api_cmd_hw_restart()
457 val = hinic_hwif_read_reg(hwif, reg_addr); in api_cmd_hw_restart()
477 u32 reg_addr, ctrl; in api_cmd_ctrl_init() local
481 reg_addr = HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(chain->chain_type); in api_cmd_ctrl_init()
486 ctrl = hinic_hwif_read_reg(hwif, reg_addr); in api_cmd_ctrl_init()
494 hinic_hwif_write_reg(hwif, reg_addr, ctrl); in api_cmd_ctrl_init()
/dpdk/drivers/crypto/ccp/
H A Dccp_dev.h154 volatile void *reg_addr = ((uint8_t *)base + offset); in ccp_pci_reg_write() local
156 rte_write32((rte_cpu_to_le_32(value)), reg_addr); in ccp_pci_reg_write()
161 volatile void *reg_addr = ((uint8_t *)base + offset); in ccp_pci_reg_read() local
163 return rte_le_to_cpu_32(rte_read32(reg_addr)); in ccp_pci_reg_read()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.h422 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
424 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
426 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
428 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
/dpdk/drivers/baseband/acc100/
H A Drte_acc100_pmd.c44 mmio_write(reg_addr, value); in acc100_reg_write()
54 uint32_t ret = *((volatile uint32_t *)(reg_addr)); in acc100_reg_read()
212 const struct acc100_registry_addr *reg_addr; in fetch_acc100_config() local
223 reg_addr = &pf_reg_addr; in fetch_acc100_config()
225 reg_addr = &vf_reg_addr; in fetch_acc100_config()
558 const struct acc100_registry_addr *reg_addr; in allocate_info_ring() local
567 reg_addr = &pf_reg_addr; in allocate_info_ring()
569 reg_addr = &vf_reg_addr; in allocate_info_ring()
602 const struct acc100_registry_addr *reg_addr; in acc100_setup_queues() local
635 reg_addr = &pf_reg_addr; in acc100_setup_queues()
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/dpdk/drivers/common/cnxk/
H A Droc_mbox.c271 uintptr_t reg_addr; in mbox_poll() local
273 reg_addr = mbox->reg_base + mbox->intr_offset; in mbox_poll()
275 rsp_reg = plt_read64(reg_addr); in mbox_poll()
287 plt_write64(rsp_reg, reg_addr); in mbox_poll()
/dpdk/drivers/baseband/fpga_lte_fec/
H A Dfpga_lte_fec.c292 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8() local
293 *((volatile uint8_t *)(reg_addr)) = payload; in fpga_reg_write_8()
300 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16() local
301 mmio_write_16(reg_addr, payload); in fpga_reg_write_16()
308 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32() local
309 mmio_write_32(reg_addr, payload); in fpga_reg_write_32()
316 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64() local
317 mmio_write_64(reg_addr, payload); in fpga_reg_write_64()
346 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32() local
356 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_8() local
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