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Searched refs:reg (Results 1 – 25 of 265) sorted by relevance

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/dpdk/lib/bpf/
H A Dbpf_exec.c19 ((type)(reg)[(ins)->dst_reg] op (type)(reg)[(ins)->src_reg]) ? \
28 ((reg)[(ins)->dst_reg] = (type)(-(reg)[(ins)->dst_reg]))
31 ((reg)[(ins)->dst_reg] = (type)(reg)[(ins)->src_reg])
34 ((reg)[(ins)->dst_reg] = \
35 (type)(reg)[(ins)->dst_reg] op (type)(reg)[(ins)->src_reg])
69 reg[ins->src_reg]))
96 v = reg + ins->dst_reg; in bpf_alu_be()
115 v = reg + ins->dst_reg; in bpf_alu_le()
457 reg[EBPF_REG_1], reg[EBPF_REG_2], in bpf_exec()
458 reg[EBPF_REG_3], reg[EBPF_REG_4], in bpf_exec()
[all …]
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_dcb_82599.c95 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
113 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599()
206 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82599() local
224 reg = 0; in ixgbe_dcb_config_tx_data_arbiter_82599()
354 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82599() local
480 u32 reg; in ixgbe_dcb_config_82599() local
495 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599()
501 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599()
510 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599()
517 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599()
[all …]
H A Dixgbe_dcb_82598.c85 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
95 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
97 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
99 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
111 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
144 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82598() local
151 reg |= IXGBE_DPMCS_TSOEF; in ixgbe_dcb_config_tx_desc_arbiter_82598()
191 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82598() local
204 reg = refill[i]; in ixgbe_dcb_config_tx_data_arbiter_82598()
234 u32 fcrtl, reg; in ixgbe_dcb_config_pfc_82598() local
[all …]
H A Dixgbe_osdep.h104 #define IXGBE_PCI_REG(reg) rte_read32(reg) argument
111 #define IXGBE_PCI_REG_WRITE(reg, value) \ argument
112 rte_write32((rte_cpu_to_le_32(value)), reg)
117 #define IXGBE_PCI_REG_WC_WRITE(reg, value) \ argument
118 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
123 #define IXGBE_PCI_REG_ADDR(hw, reg) \ argument
130 #define IXGBE_READ_PCIE_WORD(hw, reg) 0 argument
135 #define IXGBE_READ_REG(hw, reg) \ argument
138 #define IXGBE_WRITE_REG(hw, reg, value) \ argument
141 #define IXGBE_READ_REG_ARRAY(hw, reg, index) \ argument
[all …]
/dpdk/drivers/net/igc/base/
H A Digc_osdep.h81 #define IGC_PCI_REG(reg) rte_read32(reg) argument
83 #define IGC_PCI_REG16(reg) rte_read16(reg) argument
85 #define IGC_PCI_REG_WRITE(reg, value) \ argument
94 #define IGC_PCI_REG_ADDR(hw, reg) \ argument
100 #define IGC_PCI_REG_FLASH_ADDR(hw, reg) \ argument
115 #define IGC_READ_REG(hw, reg) \ argument
118 #define IGC_READ_REG_LE_VALUE(hw, reg) \ argument
121 #define IGC_WRITE_REG(hw, reg, value) \ argument
145 IGC_WRITE_REG(hw, reg, value)
151 #define IGC_READ_FLASH_REG(hw, reg) \ argument
[all …]
/dpdk/drivers/net/e1000/base/
H A De1000_osdep.h71 #define E1000_PCI_REG(reg) rte_read32(reg) argument
73 #define E1000_PCI_REG16(reg) rte_read16(reg) argument
75 #define E1000_PCI_REG_WRITE(reg, value) \ argument
76 rte_write32((rte_cpu_to_le_32(value)), reg)
84 #define E1000_PCI_REG_ADDR(hw, reg) \ argument
90 #define E1000_PCI_REG_FLASH_ADDR(hw, reg) \ argument
117 #define E1000_READ_REG(hw, reg) \ argument
120 #define E1000_WRITE_REG(hw, reg, value) \ argument
144 E1000_WRITE_REG(hw, reg, value)
150 #define E1000_READ_FLASH_REG(hw, reg) \ argument
[all …]
H A De1000_82542.c426 switch (reg) { in e1000_translate_register_82542()
428 reg = 0x00040; in e1000_translate_register_82542()
431 reg = 0x00108; in e1000_translate_register_82542()
434 reg = 0x00110; in e1000_translate_register_82542()
437 reg = 0x00114; in e1000_translate_register_82542()
440 reg = 0x00118; in e1000_translate_register_82542()
443 reg = 0x00120; in e1000_translate_register_82542()
446 reg = 0x00128; in e1000_translate_register_82542()
449 reg = 0x00138; in e1000_translate_register_82542()
452 reg = 0x0013C; in e1000_translate_register_82542()
[all …]
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_dcb_hw.c25 u32 reg = 0; in txgbe_dcb_config_rx_arbiter_raptor() local
36 wr32(hw, TXGBE_ARBRXCTL, reg); in txgbe_dcb_config_rx_arbiter_raptor()
44 reg = 0; in txgbe_dcb_config_rx_arbiter_raptor()
48 wr32(hw, TXGBE_RPUP2TC, reg); in txgbe_dcb_config_rx_arbiter_raptor()
59 reg |= TXGBE_QARBRXCFG_LSP; in txgbe_dcb_config_rx_arbiter_raptor()
87 u32 reg, max_credits; in txgbe_dcb_config_tx_desc_arbiter_raptor() local
102 reg |= TXGBE_QARBTXCFG_GSP; in txgbe_dcb_config_tx_desc_arbiter_raptor()
135 u32 reg; in txgbe_dcb_config_tx_data_arbiter_raptor() local
142 reg = TXGBE_PARBTXCTL_SP | in txgbe_dcb_config_tx_data_arbiter_raptor()
153 reg = 0; in txgbe_dcb_config_tx_data_arbiter_raptor()
[all …]
/dpdk/doc/guides/rel_notes/
H A Drelease_21_02.rst224 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
225 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
226 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 0 @ 2.70GHz
227 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
228 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v3 @ 2.30GHz
229 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v4 @ 2.20GHz
231 * Intel\ |reg| Xeon\ |reg| Gold 6139 CPU @ 2.30GHz
344 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
350 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
444 * Mellanox\ |reg| BlueField\ |reg| SmartNIC
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H A Drelease_20_08.rst269 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
270 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
271 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 0 @ 2.70GHz
272 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
276 * Intel\ |reg| Xeon\ |reg| Gold 6139 CPU @ 2.30GHz
373 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
377 * Intel\ |reg| Xeon\ |reg| CPU E5-2670 0 @ 2.60GHz
379 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
380 * Intel\ |reg| Xeon\ |reg| CPU E5-2650 0 @ 2.00GHz
467 * Mellanox\ |reg| BlueField\ |reg| SmartNIC
[all …]
H A Drelease_21_08.rst186 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
187 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
188 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
189 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v3 @ 2.30GHz
190 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v4 @ 2.20GHz
191 * Intel\ |reg| Xeon\ |reg| Gold 6140M CPU @ 2.30GHz
192 * Intel\ |reg| Xeon\ |reg| Gold 6139 CPU @ 2.30GHz
193 * Intel\ |reg| Xeon\ |reg| Gold 6252N CPU @ 2.30GHz
292 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
299 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
[all …]
H A Drelease_22_03.rst251 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
347 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
349 * Intel\ |reg| Xeon\ |reg| CPU E5-2697 v3 @ 2.60GHz
350 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
351 * Intel\ |reg| Xeon\ |reg| CPU E5-2670 0 @ 2.60GHz
352 * Intel\ |reg| Xeon\ |reg| CPU E5-2650 v4 @ 2.20GHz
353 * Intel\ |reg| Xeon\ |reg| CPU E5-2650 v3 @ 2.30GHz
354 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
355 * Intel\ |reg| Xeon\ |reg| CPU E5-2650 0 @ 2.00GHz
356 * Intel\ |reg| Xeon\ |reg| CPU E5-2620 v4 @ 2.10GHz
[all …]
H A Drelease_20_05.rst325 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
326 * Intel\ |reg| Xeon\ |reg| CPU E5-2650 v2 @ 2.60GHz
327 * Intel\ |reg| Xeon\ |reg| CPU E5-2667 v3 @ 3.20GHz
328 * Intel\ |reg| Xeon\ |reg| Gold 6142 CPU @ 2.60GHz
378 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
379 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
380 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 0 @ 2.70GHz
381 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
385 * Intel\ |reg| Xeon\ |reg| Gold 6139 CPU @ 2.30GHz
482 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
[all …]
H A Drelease_20_02.rst261 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
262 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
263 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 0 @ 2.70GHz
264 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
265 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v3 @ 2.30GHz
266 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v4 @ 2.20GHz
267 * Intel\ |reg| Xeon\ |reg| Gold 6139 CPU @ 2.30GHz
268 * Intel\ |reg| Xeon\ |reg| Gold 6252N CPU @ 2.30GHz
365 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
367 * Intel\ |reg| Xeon\ |reg| CPU E5-2697 v3 @ 2.60GHz
[all …]
H A Drelease_21_05.rst347 * Intel\ |reg| Xeon\ |reg| CPU D-1541 @ 2.10GHz
348 * Intel\ |reg| Xeon\ |reg| CPU D-1553N @ 2.30GHz
349 * Intel\ |reg| Xeon\ |reg| CPU E5-2680 v2 @ 2.80GHz
350 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v3 @ 2.30GHz
351 * Intel\ |reg| Xeon\ |reg| CPU E5-2699 v4 @ 2.20GHz
353 * Intel\ |reg| Xeon\ |reg| Gold 6139 CPU @ 2.30GHz
466 * Intel\ |reg| Xeon\ |reg| Gold 6154 CPU @ 3.00GHz
470 * Intel\ |reg| Xeon\ |reg| CPU E5-2670 0 @ 2.60GHz
473 * Intel\ |reg| Xeon\ |reg| CPU E5-2640 @ 2.50GHz
474 * Intel\ |reg| Xeon\ |reg| CPU E5-2650 0 @ 2.00GHz
[all …]
/dpdk/drivers/net/axgbe/
H A Daxgbe_mdio.c12 int reg; in axgbe_an37_clear_interrupts() local
21 int reg; in axgbe_an37_disable_interrupts() local
34 unsigned int reg; in axgbe_an37_enable_interrupts() local
721 reg |= 0x100; in axgbe_an37_init()
725 reg |= 0x80; in axgbe_an37_init()
727 reg &= ~0x80; in axgbe_an37_init()
772 reg |= 0x80; in axgbe_an73_init()
774 reg &= ~0x80; in axgbe_an73_init()
778 reg |= 0x20; in axgbe_an73_init()
780 reg &= ~0x20; in axgbe_an73_init()
[all …]
/dpdk/drivers/net/i40e/base/
H A Di40e_osdep.h138 #define I40E_PCI_REG(reg) rte_read32(reg) argument
139 #define I40E_PCI_REG_ADDR(a, reg) \ argument
146 #define I40E_PCI_REG64(reg) rte_read64(reg) argument
147 #define I40E_PCI_REG64_ADDR(a, reg) \ argument
154 #define I40E_PCI_REG_WRITE(reg, value) \ argument
159 #define I40E_PCI_REG_WC_WRITE(reg, value) \ argument
166 #define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg))) argument
167 #define I40E_WRITE_REG(hw, reg, value) \ argument
170 #define I40E_READ_REG64(hw, reg) i40e_read64_addr(I40E_PCI_REG64_ADDR((hw), (reg))) argument
172 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) argument
[all …]
/dpdk/lib/graph/
H A Dnode.c71 if (reg == NULL || reg->process == NULL) { in __rte_node_register()
90 node->flags = reg->flags; in __rte_node_register()
92 node->init = reg->init; in __rte_node_register()
93 node->fini = reg->fini; in __rte_node_register()
153 reg = calloc(1, sizeof(*reg) + (sizeof(char *) * node->nb_edges)); in node_clone()
154 if (reg == NULL) { in node_clone()
160 reg->flags = node->flags; in node_clone()
162 reg->init = node->init; in node_clone()
163 reg->fini = node->fini; in node_clone()
165 reg->parent_id = node->id; in node_clone()
[all …]
/dpdk/drivers/vdpa/ifc/base/
H A Difcvf_osdep.h22 #define IFCVF_READ_REG8(reg) rte_read8(reg) argument
23 #define IFCVF_WRITE_REG8(val, reg) rte_write8((val), (reg)) argument
24 #define IFCVF_READ_REG16(reg) rte_read16(reg) argument
25 #define IFCVF_WRITE_REG16(val, reg) rte_write16((val), (reg)) argument
26 #define IFCVF_READ_REG32(reg) rte_read32(reg) argument
27 #define IFCVF_WRITE_REG32(val, reg) rte_write32((val), (reg)) argument
/dpdk/drivers/net/vmxnet3/
H A Dvmxnet3_ethdev.h136 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg)) argument
137 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32)) argument
141 #define VMXNET3_PCI_REG(reg) rte_read32(reg) argument
149 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) argument
151 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \ argument
152 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
153 #define VMXNET3_READ_BAR0_REG(hw, reg) \ argument
155 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \ argument
158 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \ argument
160 #define VMXNET3_READ_BAR1_REG(hw, reg) \ argument
[all …]
/dpdk/drivers/common/cnxk/
H A Droc_nix_debug.c11 reg, #reg \
118 uint64_t reg; in nix_lf_gen_reg_dump() local
149 reg); in nix_lf_stat_reg_dump()
160 reg); in nix_lf_stat_reg_dump()
183 reg); in nix_lf_int_reg_dump()
194 reg); in nix_lf_int_reg_dump()
205 i, reg); in nix_lf_int_reg_dump()
216 i, reg); in nix_lf_int_reg_dump()
227 reg); in nix_lf_int_reg_dump()
238 reg); in nix_lf_int_reg_dump()
[all …]
/dpdk/drivers/common/iavf/
H A Diavf_osdep.h119 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg)) argument
120 #define rd32(a, reg) readl((a)->hw_addr + (reg)) argument
121 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg)) argument
122 #define rd64(a, reg) readq((a)->hw_addr + (reg)) argument
132 #define IAVF_PCI_REG_WRITE(reg, value) writel(value, reg) argument
133 #define IAVF_PCI_REG_WRITE_RELAXED(reg, value) writel_relaxed(value, reg) argument
135 #define IAVF_PCI_REG_WC_WRITE(reg, value) \ argument
136 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
137 #define IAVF_PCI_REG_WC_WRITE_RELAXED(reg, value) \ argument
140 #define IAVF_READ_REG(hw, reg) rd32(hw, reg) argument
[all …]
/dpdk/drivers/event/dlb2/pf/base/
H A Ddlb2_osdep.h27 #define DLB2_PCI_REG_WRITE(reg, value) rte_write32(value, (void *)reg) argument
30 #define DLB2_CSR_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->csr_kva + (reg))) argument
31 #define DLB2_CSR_RD(hw, reg) \ argument
32 DLB2_PCI_REG_READ(DLB2_CSR_REG_ADDR((hw), (reg)))
33 #define DLB2_CSR_WR(hw, reg, value) \ argument
34 DLB2_PCI_REG_WRITE(DLB2_CSR_REG_ADDR((hw), (reg)), (value))
37 #define DLB2_FUNC_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->func_kva + (reg))) argument
38 #define DLB2_FUNC_RD(hw, reg) \ argument
39 DLB2_PCI_REG_READ(DLB2_FUNC_REG_ADDR((hw), (reg)))
40 #define DLB2_FUNC_WR(hw, reg, value) \ argument
[all …]
/dpdk/drivers/net/fm10k/base/
H A Dfm10k_osdep.h58 #define FM10K_WRITE_REG(hw, reg, val) \ argument
59 rte_write32((val), ((hw)->hw_addr + (reg)))
61 #define FM10K_READ_REG(hw, reg) rte_read32(((hw)->hw_addr + (reg))) argument
65 #define FM10K_PCI_REG(reg) rte_read32(reg) argument
67 #define FM10K_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) argument
70 #define FM10K_READ_PCI_WORD(hw, reg) 0 argument
72 #define FM10K_WRITE_MBX(hw, reg, value) FM10K_WRITE_REG(hw, reg, value) argument
73 #define FM10K_READ_MBX(hw, reg) FM10K_READ_REG(hw, reg) argument
/dpdk/drivers/net/ionic/
H A Dionic_osdep.h42 #define ioread8(reg) rte_read8(reg) argument
43 #define ioread32(reg) rte_read32(rte_le_to_cpu_32(reg)) argument
44 #define iowrite8(value, reg) rte_write8(value, reg) argument
45 #define iowrite32(value, reg) rte_write32(rte_cpu_to_le_32(value), reg) argument

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