Searched refs:post (Results 1 – 11 of 11) sorted by relevance
| /dpdk/drivers/net/txgbe/base/ |
| H A D | txgbe_phy.c | 20 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode); 23 s32 post, s32 mode); 2692 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode) in txgbe_disable_kr_training() argument 2698 txgbe_read_phy_lane_tx_eq(0, hw, post, mode); in txgbe_disable_kr_training() 2763 s32 post, s32 mode) in txgbe_read_phy_lane_tx_eq() argument 2788 if (post) in txgbe_read_phy_lane_tx_eq() 2789 tx_post_cursor = post; in txgbe_read_phy_lane_tx_eq()
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| /dpdk/doc/guides/rel_notes/ |
| H A D | release_2_0.rst | 32 …The poll mode driver is also pre-release and will be updated to a released version post hardware a…
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| H A D | release_2_1.rst | 741 the pointer to NULL post-free, this caused crashes if mbuf debugging was
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| /dpdk/drivers/net/enic/ |
| H A D | enic_rxtx.c | 516 goto post; in enic_xmit_pkts() 611 post: in enic_xmit_pkts()
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| /dpdk/doc/guides/prog_guide/ |
| H A D | rte_security.rst | 73 The underlying device may support post encryption TSO. 136 to a given flow, this includes fragmented packets (post reassembly). 157 is about to overflow. The underlying device may support post encryption TSO.
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| H A D | gpudev.rst | 234 /* Do some post-processing operations. */
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| H A D | trace_lib.rst | 19 post analysis information like CPU idle time, etc that would otherwise be
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| /dpdk/doc/guides/nics/ |
| H A D | cnxk.rst | 303 plain traffic post decryption is received by ethdev. 305 2. Both Inbound encrypted traffic and plain traffic post decryption are
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| /dpdk/doc/guides/linux_gsg/ |
| H A D | build_dpdk.rst | 145 As with other meson options, this can also be set post-initial-config using `meson configure` in th…
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| /dpdk/doc/guides/contributing/ |
| H A D | vulnerability.rst | 40 Anyone can post to this list.
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| /dpdk/drivers/net/bnx2x/ |
| H A D | elink.c | 4471 #define WC_TX_FIR(post, main, pre) \ argument 4472 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
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