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Searched refs:msleep (Results 1 – 18 of 18) sorted by relevance

/dpdk/drivers/net/ixgbe/
H A Dixgbe_bypass_api.h74 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
80 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
85 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
97 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
102 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
107 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
114 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
122 msleep(IXGBE_BYPASS_BB_WAIT); in ixgbe_bypass_rw_generic()
231 msleep(100); in ixgbe_bypass_set_generic()
257 msleep(100); in ixgbe_bypass_rd_eep_generic()
H A Dixgbe_bypass_defines.h10 #define msleep(x) rte_delay_us(x*1000) macro
H A Dixgbe_bypass.c298 msleep(100); in ixgbe_bypass_ver_show()
/dpdk/drivers/raw/ifpga/base/
H A Dopae_osdep.h75 #define msleep(x) opae_udelay(1000 * (x)) macro
76 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
H A Difpga_sec_mgr.c89 msleep(interval_ms); in poll_timeout()
199 msleep(1000); in n3000_prepare()
H A Difpga_fme.c1067 msleep(100); in nios_spi_wait_init_done()
/dpdk/drivers/net/cxgbe/
H A Dcxgbe_compat.h178 #define msleep(x) DELAY(1000 * (x)) macro
179 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
/dpdk/drivers/net/i40e/base/
H A Di40e_osdep.h236 #define msleep(x) DELAY(1000*(x)) macro
237 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_mvl.c93 msleep(1); in ngbe_init_phy_mvl()
255 msleep(1); in ngbe_reset_phy_mvl()
H A Dngbe_phy_yt.c341 msleep(1); in ngbe_reset_phy_yt()
354 msleep(1); in ngbe_reset_phy_yt()
H A Dngbe_osdep.h40 #define msleep(x) rte_delay_ms(x) macro
/dpdk/drivers/net/cxgbe/base/
H A Dt4vf_hw.c30 msleep(500); in t4vf_wait_dev_ready()
152 msleep(ms); in t4vf_wr_mbox_core()
195 msleep(ms); in t4vf_wr_mbox_core()
H A Dt4_hw.c372 msleep(ms); in t4_wr_mbox_meat_timeout()
453 msleep(ms); in t4_wr_mbox_meat_timeout()
455 msleep(ms); in t4_wr_mbox_meat_timeout()
3276 msleep(50); in t4_fw_hello()
3457 msleep(100); in t4_fw_restart()
3464 msleep(2000); in t4_fw_restart()
3472 msleep(100); in t4_fw_restart()
4701 msleep(500); in t4_wait_dev_ready()
/dpdk/drivers/net/ice/base/
H A Dice_osdep.h326 #define msleep(x) DELAY(1000 * (x)) macro
327 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_osdep.h40 #define msleep(x) rte_delay_ms(x) macro
H A Dtxgbe_phy.c1464 msleep(100); in txgbe_set_link_to_kr()
1668 msleep(100); in txgbe_set_link_to_kx4()
1882 msleep(100); in txgbe_set_link_to_kx()
2121 msleep(100); in txgbe_set_link_to_sfi()
2306 msleep(1050); in txgbe_bp_down_event()
H A Dtxgbe_hw.c3283 msleep(100); in txgbe_check_flash_load()
/dpdk/drivers/net/ena/base/
H A Dena_plat_dpdk.h267 #define msleep(x) rte_delay_us(x * 1000) macro