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Searched refs:limits (Results 1 – 25 of 35) sorted by relevance

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/dpdk/drivers/vdpa/sfc/
H A Dsfc_vdpa_hw.c230 efx_drv_limits_t limits; in sfc_vdpa_estimate_resource_limits() local
237 memset(&limits, 0, sizeof(limits)); in sfc_vdpa_estimate_resource_limits()
240 limits.edl_min_rxq_count = 1; in sfc_vdpa_estimate_resource_limits()
241 limits.edl_min_txq_count = 1; in sfc_vdpa_estimate_resource_limits()
243 limits.edl_min_evq_count = in sfc_vdpa_estimate_resource_limits()
244 1 + RTE_MAX(limits.edl_min_rxq_count, limits.edl_min_txq_count); in sfc_vdpa_estimate_resource_limits()
246 limits.edl_max_rxq_count = SFC_VDPA_MAX_QUEUE_PAIRS; in sfc_vdpa_estimate_resource_limits()
250 SFC_VDPA_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count); in sfc_vdpa_estimate_resource_limits()
251 SFC_VDPA_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count); in sfc_vdpa_estimate_resource_limits()
252 SFC_VDPA_ASSERT(limits.edl_max_txq_count >= limits.edl_min_rxq_count); in sfc_vdpa_estimate_resource_limits()
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/dpdk/drivers/net/sfc/
H A Dsfc.c212 efx_drv_limits_t limits; in sfc_estimate_resource_limits() local
218 memset(&limits, 0, sizeof(limits)); in sfc_estimate_resource_limits()
224 limits.edl_min_evq_count = in sfc_estimate_resource_limits()
225 1 + limits.edl_min_rxq_count + limits.edl_min_txq_count; in sfc_estimate_resource_limits()
232 SFC_ASSERT(limits.edl_max_evq_count >= limits.edl_min_rxq_count); in sfc_estimate_resource_limits()
235 limits.edl_max_rxq_count = in sfc_estimate_resource_limits()
237 SFC_ASSERT(limits.edl_max_rxq_count >= limits.edl_min_rxq_count); in sfc_estimate_resource_limits()
239 limits.edl_max_txq_count = in sfc_estimate_resource_limits()
241 limits.edl_max_evq_count - 1 - limits.edl_max_rxq_count); in sfc_estimate_resource_limits()
244 limits.edl_max_txq_count = in sfc_estimate_resource_limits()
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H A Dsfc_ef10_essb_rx.c511 struct sfc_dp_rx_hw_limits *limits, in sfc_ef10_essb_rx_qsize_up_rings() argument
538 if (nb_hw_rx_desc <= limits->rxq_min_entries) { in sfc_ef10_essb_rx_qsize_up_rings()
539 *rxq_entries = limits->rxq_min_entries; in sfc_ef10_essb_rx_qsize_up_rings()
542 if (*rxq_entries > limits->rxq_max_entries) in sfc_ef10_essb_rx_qsize_up_rings()
552 *evq_entries = RTE_MAX(*evq_entries, limits->evq_min_entries); in sfc_ef10_essb_rx_qsize_up_rings()
553 *evq_entries = RTE_MIN(*evq_entries, limits->evq_max_entries); in sfc_ef10_essb_rx_qsize_up_rings()
H A Dsfc_dp_rx.h136 struct sfc_dp_rx_hw_limits *limits,
H A Dsfc_ef10_rx.c599 struct sfc_dp_rx_hw_limits *limits, in sfc_ef10_rx_qsize_up_rings() argument
609 if (nb_rx_desc <= limits->rxq_min_entries) in sfc_ef10_rx_qsize_up_rings()
610 *rxq_entries = limits->rxq_min_entries; in sfc_ef10_rx_qsize_up_rings()
H A Dsfc_ef100_rx.c715 struct sfc_dp_rx_hw_limits *limits, in sfc_ef100_rx_qsize_up_rings() argument
725 if (nb_rx_desc <= limits->rxq_min_entries) in sfc_ef100_rx_qsize_up_rings()
726 *rxq_entries = limits->rxq_min_entries; in sfc_ef100_rx_qsize_up_rings()
H A Dsfc_dp_tx.h108 struct sfc_dp_tx_hw_limits *limits,
H A Dsfc_ef10_tx.c910 struct sfc_dp_tx_hw_limits *limits, in sfc_ef10_tx_qsize_up_rings() argument
919 if (nb_tx_desc <= limits->txq_min_entries) in sfc_ef10_tx_qsize_up_rings()
920 *txq_entries = limits->txq_min_entries; in sfc_ef10_tx_qsize_up_rings()
H A Dsfc_ef100_tx.c814 struct sfc_dp_tx_hw_limits *limits, in sfc_ef100_tx_qsize_up_rings() argument
823 if (nb_tx_desc <= limits->txq_min_entries) in sfc_ef100_tx_qsize_up_rings()
824 *txq_entries = limits->txq_min_entries; in sfc_ef100_tx_qsize_up_rings()
H A Dsfc_mae.c220 efx_mae_limits_t limits; in sfc_mae_attach() local
237 rc = efx_mae_get_limits(sa->nic, &limits); in sfc_mae_attach()
243 limits.eml_max_n_counters); in sfc_mae_attach()
246 limits.eml_max_n_counters, rte_strerror(rc)); in sfc_mae_attach()
281 bounce_eh->buf_size = limits.eml_encap_header_size_limit; in sfc_mae_attach()
287 mae->nb_outer_rule_prios_max = limits.eml_max_n_outer_prios; in sfc_mae_attach()
288 mae->nb_action_rule_prios_max = limits.eml_max_n_action_prios; in sfc_mae_attach()
289 mae->encap_types_supported = limits.eml_encap_types_supported; in sfc_mae_attach()
H A Dsfc_tx.c1072 __rte_unused struct sfc_dp_tx_hw_limits *limits, in sfc_efx_tx_qsize_up_rings() argument
/dpdk/app/test-eventdev/
H A Dtest_pipeline_common.c364 memset(&limits, 0, sizeof(limits)); in pipeline_event_rx_adapter_setup()
366 opt->dev_id, prod, &limits); in pipeline_event_rx_adapter_setup()
372 if (opt->vector_size < limits.min_sz || in pipeline_event_rx_adapter_setup()
373 opt->vector_size > limits.max_sz) { in pipeline_event_rx_adapter_setup()
375 opt->vector_size, limits.min_sz, in pipeline_event_rx_adapter_setup()
376 limits.max_sz); in pipeline_event_rx_adapter_setup()
380 if (limits.log2_sz && in pipeline_event_rx_adapter_setup()
387 if (opt->vector_tmo_nsec > limits.max_timeout_ns || in pipeline_event_rx_adapter_setup()
388 opt->vector_tmo_nsec < limits.min_timeout_ns) { in pipeline_event_rx_adapter_setup()
393 limits.max_timeout_ns, in pipeline_event_rx_adapter_setup()
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/dpdk/drivers/common/sfc_efx/base/
H A Dmcdi_mon.c344 efx_mon_stat_limits_t *limits)
355 EFSYS_ASSERT(limits != NULL);
357 memset(limits, 0,
393 limits->emlv_warning_min = EFX_QWORD_FIELD(*limit_info,
396 limits->emlv_warning_max = EFX_QWORD_FIELD(*limit_info,
399 limits->emlv_fatal_min = EFX_QWORD_FIELD(*limit_info,
402 limits->emlv_fatal_max = EFX_QWORD_FIELD(*limit_info,
405 limits++;
486 efx_mon_stat_limits_t limits[sizeof (page_mask) * 8]; in mcdi_mon_limits_update() local
494 rc = efx_mcdi_sensor_info_page(enp, page, &page_mask, limits); in mcdi_mon_limits_update()
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/dpdk/examples/ipsec-secgw/
H A Devent_helper.c749 struct rte_event_eth_rx_adapter_vector_limits limits = {0}; in eh_event_vector_limits_validate() local
754 &limits); in eh_event_vector_limits_validate()
760 if (vector_size < limits.min_sz || vector_size > limits.max_sz) { in eh_event_vector_limits_validate()
762 vector_size, limits.min_sz, limits.max_sz); in eh_event_vector_limits_validate()
766 if (limits.log2_sz && !rte_is_power_of_2(vector_size)) { in eh_event_vector_limits_validate()
771 if (em_conf->vector_tmo_ns > limits.max_timeout_ns || in eh_event_vector_limits_validate()
772 em_conf->vector_tmo_ns < limits.min_timeout_ns) { in eh_event_vector_limits_validate()
777 limits.max_timeout_ns, in eh_event_vector_limits_validate()
778 limits.min_timeout_ns); in eh_event_vector_limits_validate()
/dpdk/doc/guides/linux_gsg/
H A Denable_func.rst24 When running as non-root user, there may be some additional resource limits
25 that are imposed by the system. Specifically, the following resource limits may
34 The above limits can usually be adjusted by editing
35 ``/etc/security/limits.conf`` file, and rebooting.
H A Deal_args.include.rst216 Specify the maximum SIMD bitwidth size to handle. This limits which vector paths,
/dpdk/drivers/event/cnxk/
H A Dcn10k_eventdev.c754 struct rte_event_eth_rx_adapter_vector_limits *limits) in cn10k_sso_rx_adapter_vector_limits() argument
765 limits->log2_sz = true; in cn10k_sso_rx_adapter_vector_limits()
766 limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2; in cn10k_sso_rx_adapter_vector_limits()
767 limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2; in cn10k_sso_rx_adapter_vector_limits()
768 limits->min_timeout_ns = in cn10k_sso_rx_adapter_vector_limits()
770 limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns; in cn10k_sso_rx_adapter_vector_limits()
/dpdk/lib/eventdev/
H A Drte_event_eth_rx_adapter.c2562 struct rte_event_eth_rx_adapter_vector_limits limits; in rte_event_eth_rx_adapter_queue_add() local
2602 rx_adapter->eventdev_id, eth_dev_id, &limits); in rte_event_eth_rx_adapter_queue_add()
2610 if (queue_conf->vector_sz < limits.min_sz || in rte_event_eth_rx_adapter_queue_add()
2611 queue_conf->vector_sz > limits.max_sz || in rte_event_eth_rx_adapter_queue_add()
2705 limits->max_sz = MAX_VECTOR_SIZE; in rxa_sw_vector_limits()
2706 limits->min_sz = MIN_VECTOR_SIZE; in rxa_sw_vector_limits()
2707 limits->max_timeout_ns = MAX_VECTOR_NS; in rxa_sw_vector_limits()
2708 limits->min_timeout_ns = MIN_VECTOR_NS; in rxa_sw_vector_limits()
2850 if (limits == NULL) in rte_event_eth_rx_adapter_vector_limits_get()
2868 dev, &rte_eth_devices[eth_port_id], limits); in rte_event_eth_rx_adapter_vector_limits_get()
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H A Drte_event_eth_rx_adapter.h613 struct rte_event_eth_rx_adapter_vector_limits *limits);
H A Deventdev_pmd.h889 struct rte_event_eth_rx_adapter_vector_limits *limits);
/dpdk/doc/guides/faq/
H A Dfaq.rst126 … which can result in reaching the open files limits, which is set using the ulimit command or in t…
128 This can be done either by issuing a ulimit command or editing the limits.conf file. Please consult…
/dpdk/doc/guides/eventdevs/
H A Docteontx.rst111 and they can be configured by passing limits to kernel bootargs as follows:
/dpdk/doc/guides/prog_guide/
H A Dreorder_lib.rst23 number of 350, the sequence window has low and high limits of 350 and 550
/dpdk/doc/guides/sample_app_ug/
H A Dip_reassembly.rst152 To keep mempool size under reasonable limits and to avoid situation when one RX queue can starve ot…
/dpdk/doc/guides/nics/
H A Dmlx5.rst236 - Hardware limits ``header_length_mask_width`` up to 6 bits.
307 amount may exceed the hardware supported limits. The application should
716 queue size limits supported by hardware may be exceeded.
728 by the driver in order not to exceed the limits and provide better descriptor
824 Maximum size of packet to be inlined. This limits the size of packet to

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