| /dpdk/drivers/common/mlx5/ |
| H A D | mlx5_prm.h | 798 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) argument
803 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) argument
804 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) argument
805 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ argument
808 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) argument
812 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ argument
816 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) argument
851 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
855 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
859 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
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| /dpdk/drivers/net/ice/base/ |
| H A D | ice_flow.c | 1376 switch (fld) { in ice_flow_xtract_fld()
1541 flds[fld].xtrct.off = (ice_flds_info[fld].off / ese_bits) * in ice_flow_xtract_fld()
1543 flds[fld].xtrct.disp = (u8)(ice_flds_info[fld].off % ese_bits); in ice_flow_xtract_fld()
1545 flds[fld].xtrct.mask = ice_flds_info[fld].mask; in ice_flow_xtract_fld()
1554 off = flds[fld].xtrct.off; in ice_flow_xtract_fld()
1555 mask = flds[fld].xtrct.mask; in ice_flow_xtract_fld()
1772 fld->xtrct.disp, in ice_flow_acl_def_entry_frmt()
1781 fld->entry.val = range_idx++; in ice_flow_acl_def_entry_frmt()
1791 fld->entry.val = index; in ice_flow_acl_def_entry_frmt()
1792 index += fld->entry.last; in ice_flow_acl_def_entry_frmt()
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| H A D | ice_flow.h | 581 ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
584 ice_flow_set_fld_prefix(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
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| H A D | ice_protocol_type.h | 274 } fld; member
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| H A D | ice_flex_type.h | 898 } fld; member
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| /dpdk/app/test-pmd/ |
| H A D | cmd_flex_item.c | 75 flex_field_parse(json_t *jfld, struct rte_flow_item_flex_field *fld) in flex_field_parse() argument
84 fld->fm = (t) json_real_value(je); \ in flex_field_parse()
86 fld->fm = (t) json_integer_value(je); \ in flex_field_parse()
105 fld->field_mode = FIELD_MODE_DUMMY; in flex_field_parse()
107 fld->field_mode = FIELD_MODE_FIXED; in flex_field_parse()
109 fld->field_mode = FIELD_MODE_OFFSET; in flex_field_parse()
111 fld->field_mode = FIELD_MODE_BITMASK; in flex_field_parse()
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| /dpdk/drivers/net/bnxt/tf_ulp/ |
| H A D | ulp_mapper.c | 1369 struct bnxt_ulp_mapper_field_info *fld, in ulp_mapper_field_opc_process() argument
1384 switch (fld->field_opc) { in ulp_mapper_field_opc_process()
1418 fld->field_opr1, dir, is_key, in ulp_mapper_field_opc_process()
1419 fld->field_bit_size, &val1, in ulp_mapper_field_opc_process()
1444 fld->field_opr2, dir, is_key, in ulp_mapper_field_opc_process()
1445 fld->field_bit_size, &val2, in ulp_mapper_field_opc_process()
1462 fld->field_opr3, dir, is_key, in ulp_mapper_field_opc_process()
1463 fld->field_bit_size, &val3, in ulp_mapper_field_opc_process()
1477 val_len = fld->field_bit_size; in ulp_mapper_field_opc_process()
1479 switch (fld->field_opc) { in ulp_mapper_field_opc_process()
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| /dpdk/lib/acl/ |
| H A D | acl_bld.c | 950 const struct rte_acl_field *fld; in build_trie() local
968 fld = rule->f->field + field_index; in build_trie()
976 &fld->value, in build_trie()
977 &fld->mask_range, in build_trie()
991 fld->mask_range.u32, in build_trie()
996 &fld->value, in build_trie()
1086 const struct rte_acl_field *fld = rule->f->field + in acl_calc_wildness() local
1092 fld->mask_range.u64 & msk_val)) / in acl_calc_wildness()
1097 wild = (size - fld->mask_range.u32) / size; in acl_calc_wildness()
1101 wild = (fld->mask_range.u64 & msk_val) - in acl_calc_wildness()
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| /dpdk/drivers/net/nfp/ |
| H A D | nfp_rxtx.c | 68 rxd->fld.dd = 0; in nfp_net_rx_fill_freelist()
69 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff; in nfp_net_rx_fill_freelist()
70 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff; in nfp_net_rx_fill_freelist()
416 rxds->fld.dd = 0; in nfp_net_recv_pkts()
417 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff; in nfp_net_recv_pkts()
418 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff; in nfp_net_recv_pkts()
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| H A D | nfp_rxtx.h | 179 } __rte_packed fld; member
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| /dpdk/drivers/net/enic/base/ |
| H A D | vnic_devcmd.h | 775 #define FILTER_FIELD_VALID(fld) (1 << (fld - 1)) argument
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| /dpdk/drivers/net/ice/ |
| H A D | ice_switch_filter.c | 814 vtf.u.fld.version = 0; in ice_switch_parse_pattern()
815 vtf.u.fld.flow_label = 0; in ice_switch_parse_pattern()
816 vtf.u.fld.tc = (rte_be_to_cpu_32 in ice_switch_parse_pattern()
821 vtf.u.fld.tc = (rte_be_to_cpu_32 in ice_switch_parse_pattern()
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| H A D | ice_fdir_filter.c | 919 enum ice_flow_field fld; in ice_fdir_input_set_parse() member
960 field[j++] = ice_inset_map[i].fld; in ice_fdir_input_set_parse()
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| H A D | ice_ethdev.c | 605 #define FLX_REG(val, fld, idx) \ in ice_check_proto_xtr_support() argument
606 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \ in ice_check_proto_xtr_support()
607 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S) in ice_check_proto_xtr_support()
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| /dpdk/drivers/net/iavf/ |
| H A D | iavf_hash.c | 872 #define REFINE_PROTO_FLD(op, fld) \ argument
873 VIRTCHNL_##op##_PROTO_HDR_FIELD(hdr, VIRTCHNL_PROTO_HDR_##fld)
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| /dpdk/drivers/net/mlx5/ |
| H A D | mlx5_flow.c | 260 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ in mlx5_flow_expand_rss_item_complete() argument
265 ((const struct rte_flow_item_##type *)m)->fld : \ in mlx5_flow_expand_rss_item_complete()
266 rte_flow_item_##type##_mask.fld; \ in mlx5_flow_expand_rss_item_complete()
267 spec = ((const struct rte_flow_item_##type *)s)->fld; \ in mlx5_flow_expand_rss_item_complete()
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