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/dpdk/drivers/net/pfe/
H A Dpfe_hal.c169 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base in gemac_set_duplex()
171 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base in gemac_set_duplex()
174 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base in gemac_set_duplex()
176 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base in gemac_set_duplex()
225 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + in gemac_tx_disable()
232 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base + in gemac_tx_enable()
299 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + in gemac_set_loop()
309 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + in gemac_enable_copy_all()
319 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + in gemac_disable_copy_all()
339 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + in gemac_no_broadcast()
[all …]
/dpdk/drivers/net/bnx2x/
H A Decore_fw_defs.h28 (IRO[163].base + ((funcId) * IRO[163].m1))
30 (IRO[153].base + ((funcId) * IRO[153].m1))
38 (IRO[323].base + ((pfId) * IRO[323].m1))
40 (IRO[324].base + ((pfId) * IRO[324].m1))
56 (IRO[322].base + ((pfId) * IRO[322].m1))
58 (IRO[314].base + ((pfId) * IRO[314].m1))
60 (IRO[313].base + ((pfId) * IRO[313].m1))
62 (IRO[312].base + ((pfId) * IRO[312].m1))
66 (IRO[146].base + ((pfId) * IRO[146].m1))
68 (IRO[147].base + ((pfId) * IRO[147].m1))
[all …]
/dpdk/drivers/net/qede/base/
H A Decore_iro.h11 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
42 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
45 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
48 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
51 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
54 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
57 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
83 (IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
87 (IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
91 (IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
[all …]
/dpdk/drivers/net/pfe/base/
H A Dpfe.h299 void bmu_reset(void *base);
300 void bmu_enable(void *base);
301 void bmu_disable(void *base);
321 void gemac_enable(void *base);
322 void gemac_tx_disable(void *base);
323 void gemac_tx_enable(void *base);
324 void gemac_disable(void *base);
325 void gemac_reset(void *base);
367 void gpi_reset(void *base);
368 void gpi_enable(void *base);
[all …]
/dpdk/drivers/common/cnxk/
H A Droc_sso_debug.c9 sso_hws_dump(uintptr_t base, FILE *f) in sso_hws_dump() argument
13 plt_read64(base + SSOW_LF_GWS_LINKS)); in sso_hws_dump()
15 plt_read64(base + SSOW_LF_GWS_PENDWQP)); in sso_hws_dump()
21 plt_read64(base + SSOW_LF_GWS_TAG)); in sso_hws_dump()
23 plt_read64(base + SSOW_LF_GWS_TAG)); in sso_hws_dump()
25 plt_read64(base + SSOW_LF_GWS_SWTP)); in sso_hws_dump()
31 sso_hwgrp_dump(uintptr_t base, FILE *f) in sso_hwgrp_dump() argument
35 plt_read64(base + SSO_LF_GGRP_QCTL)); in sso_hwgrp_dump()
54 uintptr_t base; in roc_sso_dump() local
60 sso_hws_dump(base, f); in roc_sso_dump()
[all …]
H A Droc_tim_irq.c11 uintptr_t base = (uintptr_t)param; in tim_lf_irq() local
15 ring = (base >> 12) & 0xFF; in tim_lf_irq()
17 intr = plt_read64(base + TIM_LF_NRSPERR_INT); in tim_lf_irq()
19 intr = plt_read64(base + TIM_LF_RAS_INT); in tim_lf_irq()
23 plt_write64(intr, base + TIM_LF_NRSPERR_INT); in tim_lf_irq()
24 plt_write64(intr, base + TIM_LF_RAS_INT); in tim_lf_irq()
37 plt_write64(~0ull, base + TIM_LF_NRSPERR_INT); in tim_lf_register_irq()
46 plt_write64(~0ull, base + TIM_LF_RAS_INT); in tim_lf_register_irq()
50 plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S); in tim_lf_register_irq()
60 uintptr_t base; in tim_register_irq_priv() local
[all …]
H A Droc_npa_irq.c14 intr = plt_read64(lf->base + NPA_LF_ERR_INT); in npa_err_irq()
21 plt_write64(intr, lf->base + NPA_LF_ERR_INT); in npa_err_irq()
62 intr = plt_read64(lf->base + NPA_LF_RAS); in npa_ras_irq()
69 plt_write64(intr, lf->base + NPA_LF_RAS); in npa_ras_irq()
81 plt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C); in npa_register_ras_irq()
85 plt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S); in npa_register_ras_irq()
99 plt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C); in npa_unregister_ras_irq()
120 plt_write64(wdata | qint, lf->base + off); in npa_q_irq_get_and_clear()
211 plt_write64(0, lf->base + NPA_LF_QINTX_CNT(q)); in npa_register_queue_irqs()
231 plt_write64(0, lf->base + NPA_LF_QINTX_CNT(q)); in npa_register_queue_irqs()
[all …]
H A Droc_sso_irq.c14 intr = plt_read64(rsrc->base + SSO_LF_GGRP_INT); in sso_hwgrp_irq()
21 plt_write64(intr, rsrc->base + SSO_LF_GGRP_INT); in sso_hwgrp_irq()
33 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1C); in sso_hwgrp_register_irq()
37 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1S); in sso_hwgrp_register_irq()
48 intr = plt_read64(rsrc->base + SSOW_LF_GWS_INT); in sso_hws_irq()
55 plt_write64(intr, rsrc->base + SSOW_LF_GWS_INT); in sso_hws_irq()
67 plt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1C); in sso_hws_register_irq()
101 uintptr_t base = in sso_register_irqs_priv() local
105 sso->hws_rsrc[i].base = base; in sso_register_irqs_priv()
111 uintptr_t base = in sso_register_irqs_priv() local
[all …]
H A Droc_nix_irq.c14 nix->base + NIX_LF_ERR_INT_ENA_W1S); in nix_err_intr_enb_dis()
23 plt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1S); in nix_ras_intr_enb_dis()
25 plt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1C); in nix_ras_intr_enb_dis()
69 intr = plt_read64(nix->base + NIX_LF_ERR_INT); in nix_lf_err_irq()
76 plt_write64(intr, nix->base + NIX_LF_ERR_INT); in nix_lf_err_irq()
118 intr = plt_read64(nix->base + NIX_LF_RAS); in nix_lf_ras_irq()
124 plt_write64(intr, nix->base + NIX_LF_RAS); in nix_lf_ras_irq()
176 plt_write64(wdata | qint, nix->base + off); in nix_lf_q_irq_get_and_clear()
227 reg = plt_read64(nix->base + off); in nix_lf_sq_debug_reg()
231 plt_write64(BIT_ULL(44), nix->base + off); in nix_lf_sq_debug_reg()
[all …]
H A Dcnxk_security_ar.h29 uint64_t base; /**< base of the anti-replay window */ member
61 uint64_t base = ar->base; in cnxk_on_anti_replay_check() local
74 if (likely(seq > base)) { in cnxk_on_anti_replay_check()
75 shift = seq - base; in cnxk_on_anti_replay_check()
107 ar->base = seq; in cnxk_on_anti_replay_check()
111 bit_pos = base - seq; in cnxk_on_anti_replay_check()
130 if (likely(seq > base)) { in cnxk_on_anti_replay_check()
133 shift = seq - base; in cnxk_on_anti_replay_check()
158 ar->base = seq; in cnxk_on_anti_replay_check()
181 if (unlikely((seq + winsz) <= base)) in cnxk_on_anti_replay_check()
H A Droc_ree.c424 uintptr_t base = (uintptr_t)param; in roc_ree_lf_err_intr_handler() local
428 lf_id = (base >> 12) & 0xFF; in roc_ree_lf_err_intr_handler()
442 uintptr_t base) in roc_ree_lf_err_intr_unregister() argument
456 uintptr_t base; in roc_ree_err_intr_unregister() local
460 base = REE_LF_BAR2(vf, i); in roc_ree_err_intr_unregister()
469 uintptr_t base) in roc_ree_lf_err_intr_register() argument
494 uintptr_t base; in roc_ree_err_intr_register() local
505 base = REE_LF_BAR2(vf, i); in roc_ree_err_intr_register()
517 base = REE_LF_BAR2(vf, j); in roc_ree_err_intr_register()
542 val = plt_read64(qp->base + REE_LF_ENA); in roc_ree_iq_enable()
[all …]
H A Droc_nix_inl.h65 roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx) in roc_nix_inl_onf_ipsec_inb_sa() argument
69 return PLT_PTR_ADD(base, off); in roc_nix_inl_onf_ipsec_inb_sa()
73 roc_nix_inl_onf_ipsec_outb_sa(uintptr_t base, uint64_t idx) in roc_nix_inl_onf_ipsec_outb_sa() argument
77 return PLT_PTR_ADD(base, off); in roc_nix_inl_onf_ipsec_outb_sa()
93 roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx) in roc_nix_inl_ot_ipsec_inb_sa() argument
97 return PLT_PTR_ADD(base, off); in roc_nix_inl_ot_ipsec_inb_sa()
101 roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx) in roc_nix_inl_ot_ipsec_outb_sa() argument
105 return PLT_PTR_ADD(base, off); in roc_nix_inl_ot_ipsec_outb_sa()
/dpdk/drivers/bus/dpaa/
H A Dmeson.build11 'base/fman/fman.c',
12 'base/fman/fman_hw.c',
13 'base/fman/netcfg_layer.c',
14 'base/qbman/bman.c',
15 'base/qbman/bman_driver.c',
16 'base/qbman/dpaa_alloc.c',
17 'base/qbman/dpaa_sys.c',
18 'base/qbman/process.c',
19 'base/qbman/qman.c',
20 'base/qbman/qman_driver.c',
[all …]
/dpdk/app/test/
H A Dtest_cryptodev_mod_test_vectors.h17 } base; member
38 } base; member
56 .base = {
118 .base = {
172 .base = {
212 .base = {
307 .base = {
402 .base = {
495 .base = {
668 .base = {
[all …]
/dpdk/drivers/event/cnxk/
H A Dcn9k_worker.h57 cnxk_sso_hws_swtag_untag(base + in cn9k_sso_hws_fwd_swtag()
96 roc_sso_hws_head_wait(ws->base); in cn9k_sso_hws_forward_event()
145 cn9k_sso_hws_fwd_swtag(base, ev); in cn9k_sso_hws_dual_forward_event()
154 roc_sso_hws_head_wait(base); in cn9k_sso_hws_dual_forward_event()
547 dws->base[!dws->vws], \
685 if (base) in cn9k_sso_hws_xmit_sec_one()
686 roc_sso_hws_head_wait(base); in cn9k_sso_hws_xmit_sec_one()
726 RTE_SET_USED(base); in cn9k_sso_hws_xmit_sec_one()
760 uintptr_t ssow_base = base; in cn9k_sso_hws_event_tx()
780 roc_sso_hws_head_wait(base); in cn9k_sso_hws_event_tx()
[all …]
H A Dcn9k_worker.c23 cnxk_sso_hws_desched(ev->u64, ws->base); in cn9k_sso_hws_enq()
27 cnxk_sso_hws_swtag_flush(ws->base); in cn9k_sso_hws_enq()
75 uint64_t base; in cn9k_sso_hws_dual_enq() local
77 base = dws->base[!dws->vws]; in cn9k_sso_hws_dual_enq()
82 cn9k_sso_hws_dual_forward_event(dws, base, ev); in cn9k_sso_hws_dual_enq()
86 cnxk_sso_hws_desched(ev->u64, base); in cn9k_sso_hws_dual_enq()
90 cnxk_sso_hws_swtag_flush(base); in cn9k_sso_hws_dual_enq()
127 cn9k_sso_hws_dual_forward_event(dws, dws->base[!dws->vws], ev); in cn9k_sso_hws_dual_enq_fwd_burst()
139 return cn9k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr); in cn9k_sso_hws_ca_enq()
149 return cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws], in cn9k_sso_hws_dual_ca_enq()
H A Dcn10k_eventdev.c123 plt_write64(0, base + SSO_LF_GGRP_QCTL); in cn10k_sso_hws_flush_events()
130 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT); in cn10k_sso_hws_flush_events()
144 cnxk_sso_hws_swtag_flush(ws->base); in cn10k_sso_hws_flush_events()
171 uintptr_t base = ws->base; in cn10k_sso_hws_reset() local
196 cnxk_sso_hws_swtag_untag(base + in cn10k_sso_hws_reset()
220 ws->base + SSOW_LF_GWS_OP_GET_WORK0); in cn10k_sso_hws_reset()
223 ws->base + SSOW_LF_GWS_WQE0); in cn10k_sso_hws_reset()
230 base + SSOW_LF_GWS_OP_SWTAG_UNTAG); in cn10k_sso_hws_reset()
573 cnxk_sso_hws_swtag_flush(ws->base); in cn10k_sso_port_quiesce()
592 ws->base + SSOW_LF_GWS_OP_GET_WORK0); in cn10k_sso_port_quiesce()
[all …]
H A Dcnxk_worker.h48 cnxk_sso_hws_swtag_flush(uint64_t base) in cnxk_sso_hws_swtag_flush() argument
51 while (plt_read64(base + SSOW_LF_GWS_PENDSTATE) & BIT_ULL(56)) in cnxk_sso_hws_swtag_flush()
53 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_TAG)) == in cnxk_sso_hws_swtag_flush()
56 plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH); in cnxk_sso_hws_swtag_flush()
86 cnxk_sso_hws_desched(uint64_t u64, uint64_t base) in cnxk_sso_hws_desched() argument
88 plt_write64(u64, base + SSOW_LF_GWS_OP_UPD_WQP_GRP1); in cnxk_sso_hws_desched()
89 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED); in cnxk_sso_hws_desched()
H A Dcn9k_eventdev.c137 plt_write64(0, base + SSO_LF_GGRP_QCTL); in cn9k_sso_hws_flush_events()
150 ws_base = dws->base[0]; in cn9k_sso_hws_flush_events()
155 ws_base = ws->base; in cn9k_sso_hws_flush_events()
196 uintptr_t base; in cn9k_sso_hws_reset() local
204 base = dev->dual_ws ? dws->base[i] : ws->base; in cn9k_sso_hws_reset()
224 base + SSOW_LF_GWS_OP_SWTAG_UNTAG); in cn9k_sso_hws_reset()
699 dws->base[0] = roc_sso_hws_base_get( in cn9k_sso_init_hws_mem()
701 dws->base[1] = roc_sso_hws_base_get( in cn9k_sso_init_hws_mem()
823 uintptr_t base; in cn9k_sso_port_quiesce() local
831 base = dev->dual_ws ? dws->base[i] : ws->base; in cn9k_sso_port_quiesce()
[all …]
/dpdk/lib/eal/freebsd/include/
H A Drte_os_shim.h21 rte_timespec_get(struct timespec *now, int base) in rte_timespec_get() argument
23 if (base != TIME_UTC || clock_gettime(CLOCK_REALTIME, now) < 0) in rte_timespec_get()
25 return base; in rte_timespec_get()
28 #define timespec_get(ts, base) rte_timespec_get(ts, base) argument
/dpdk/drivers/net/enic/
H A Dmeson.build11 'base/vnic_cq.c',
12 'base/vnic_dev.c',
13 'base/vnic_intr.c',
14 'base/vnic_rq.c',
15 'base/vnic_wq.c',
25 includes += include_directories('base')
/dpdk/drivers/bus/dpaa/base/qbman/
H A Dprocess.c44 uint32_t base; /* Return value, the start of the allocated range */ member
54 uint32_t base; member
60 uint32_t base; member
71 int process_alloc(enum dpaa_id_type id_type, uint32_t *base, uint32_t num, in process_alloc() argument
88 base[ret] = id.base + ret; in process_alloc()
92 void process_release(enum dpaa_id_type id_type, uint32_t base, uint32_t num) in process_release() argument
96 .base = base, in process_release()
108 id_type, base, num); in process_release()
111 int process_reserve(enum dpaa_id_type id_type, uint32_t base, uint32_t num) in process_reserve() argument
115 .base = base, in process_reserve()
/dpdk/drivers/net/ena/
H A Dmeson.build13 'base/ena_com.c',
14 'base/ena_eth_com.c',
19 includes += include_directories('base', 'base/ena_defs')
/dpdk/lib/eal/windows/include/
H A Drte_os_shim.h55 rte_timespec_get(struct timespec *now, int base) in rte_timespec_get() argument
65 if (base != TIME_UTC) in rte_timespec_get()
73 return base; in rte_timespec_get()
76 #define timespec_get(ts, base) rte_timespec_get(ts, base) argument
/dpdk/drivers/net/vmxnet3/
H A Dvmxnet3_rxtx.c80 rxq->cmd_ring[0].base, rxq->cmd_ring[1].base, rxq->comp_ring.base); in vmxnet3_rxq_dump()
110 txq->cmd_ring.base, txq->comp_ring.base, txq->data_ring.base); in vmxnet3_txq_dump()
231 memset(ring->base, 0, size); in vmxnet3_dev_tx_queue_reset()
268 memset(ring0->base, 0, size); in vmxnet3_dev_rx_queue_reset()
1094 ring->base = mz->addr; in vmxnet3_dev_tx_queue_setup()
1098 comp_ring->base = ring->base + ring->size; in vmxnet3_dev_tx_queue_setup()
1103 data_ring->base = (Vmxnet3_TxDataDesc *)(comp_ring->base + comp_ring->size); in vmxnet3_dev_tx_queue_setup()
1205 ring0->base = mz->addr; in vmxnet3_dev_rx_queue_setup()
1209 ring1->base = ring0->base + ring0->size; in vmxnet3_dev_rx_queue_setup()
1213 comp_ring->base = ring1->base + ring1->size; in vmxnet3_dev_rx_queue_setup()
[all …]

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