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Searched refs:RTE_BE32 (Results 1 – 20 of 20) sorted by relevance

/dpdk/app/test-flow-perf/
H A Ditems_gen.c59 ipv4_specs[ti].hdr.src_addr = RTE_BE32(para.src_ip); in add_ipv4()
60 ipv4_masks[ti].hdr.src_addr = RTE_BE32(0xffffffff); in add_ipv4()
216 .teid = RTE_BE32(TEID_VALUE), in add_gtp()
219 .teid = RTE_BE32(0xffffffff), in add_gtp()
233 .data = RTE_BE32(META_DATA), in add_meta_data()
236 .data = RTE_BE32(0xffffffff), in add_meta_data()
251 .data = RTE_BE32(META_DATA), in add_meta_tag()
255 .data = RTE_BE32(0xffffffff), in add_meta_tag()
H A Dactions_gen.c149 .data = RTE_BE32(META_DATA), in add_set_meta()
150 .mask = RTE_BE32(0xffffffff), in add_set_meta()
163 .data = RTE_BE32(META_DATA), in add_set_tag()
164 .mask = RTE_BE32(0xffffffff), in add_set_tag()
390 value[para.core_idx] = RTE_BE32(ack_value); in add_inc_tcp_ack()
408 value[para.core_idx] = RTE_BE32(ack_value); in add_dec_tcp_ack()
426 value[para.core_idx] = RTE_BE32(seq_value); in add_inc_tcp_seq()
444 value[para.core_idx] = RTE_BE32(seq_value); in add_dec_tcp_seq()
588 ipv4_hdr.dst_addr = RTE_BE32(ip_dst); in add_ipv4_header()
741 gtp_hdr.teid = RTE_BE32(teid_value); in add_gtp_header()
[all …]
/dpdk/drivers/net/mlx5/
H A Dmlx5_txpp.c191 cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0); in mlx5_txpp_fill_wqe_rearm_queue()
193 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << in mlx5_txpp_fill_wqe_rearm_queue()
195 cs->misc = RTE_BE32(0); in mlx5_txpp_fill_wqe_rearm_queue()
204 cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0); in mlx5_txpp_fill_wqe_rearm_queue()
206 cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR << in mlx5_txpp_fill_wqe_rearm_queue()
208 cs->misc = RTE_BE32(0); in mlx5_txpp_fill_wqe_rearm_queue()
307 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET); in mlx5_txpp_fill_wqe_clock_queue()
308 cs->misc = RTE_BE32(0); in mlx5_txpp_fill_wqe_clock_queue()
346 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) | in mlx5_txpp_fill_wqe_clock_queue()
348 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) | in mlx5_txpp_fill_wqe_clock_queue()
H A Dmlx5_flow_aso.c132 wqe->aso_cseg.operand_masks = RTE_BE32(0u | in mlx5_aso_mtr_init_sq()
137 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS << in mlx5_aso_mtr_init_sq()
174 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS << in mlx5_aso_ct_init_sq()
374 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR << in mlx5_aso_sq_enqueue_burst()
387 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS << in mlx5_aso_sq_enqueue_burst()
687 RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL); in mlx5_aso_mtr_sq_enqueue_single()
693 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) | in mlx5_aso_mtr_sq_enqueue_single()
698 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) | in mlx5_aso_mtr_sq_enqueue_single()
705 RTE_BE32(1 << ASO_DSEG_BO_OFFSET); in mlx5_aso_mtr_sq_enqueue_single()
709 RTE_BE32(1 << ASO_DSEG_BBOG_OFFSET); in mlx5_aso_mtr_sq_enqueue_single()
H A Dmlx5_tx.h709 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS << in mlx5_tx_request_completion()
760 cs->misc = RTE_BE32(0); in mlx5_tx_cseg_init()
790 qs->reserved0 = RTE_BE32(0); in mlx5_tx_qseg_init()
791 qs->reserved1 = RTE_BE32(0); in mlx5_tx_qseg_init()
820 ws->lkey = RTE_BE32(0); in mlx5_tx_wseg_init()
821 ws->va_high = RTE_BE32(0); in mlx5_tx_wseg_init()
822 ws->va_low = RTE_BE32(0); in mlx5_tx_wseg_init()
881 es->inline_hdr = RTE_BE32(0); in mlx5_tx_eseg_none()
1893 wqe->cseg.sq_ds -= RTE_BE32(1); in mlx5_tx_packet_multi_send()
2866 dseg->bcount = RTE_BE32(0); in mlx5_tx_burst_empw_inline()
[all …]
H A Dmlx5_flow_dv.c1599 mask[3] = RTE_BE32(0xffffffff); in mlx5_flow_field_id_to_modify_info()
1615 mask[2] = RTE_BE32(0xffffffff); in mlx5_flow_field_id_to_modify_info()
1631 mask[1] = RTE_BE32(0xffffffff); in mlx5_flow_field_id_to_modify_info()
1667 mask[3] = RTE_BE32(0xffffffff); in mlx5_flow_field_id_to_modify_info()
1683 mask[2] = RTE_BE32(0xffffffff); in mlx5_flow_field_id_to_modify_info()
1699 mask[1] = RTE_BE32(0xffffffff); in mlx5_flow_field_id_to_modify_info()
2090 .data = RTE_BE32(UINT32_MAX), in flow_dv_validate_item_tag()
2326 .teid = RTE_BE32(0xffffffff), in flow_dv_validate_item_gtp()
2446 .src_addr = RTE_BE32(0xffffffff), in flow_dv_validate_item_ipv4()
2447 .dst_addr = RTE_BE32(0xffffffff), in flow_dv_validate_item_ipv4()
[all …]
H A Dmlx5_flow.c2470 .src_addr = RTE_BE32(0xffffffff), in mlx5_flow_validate_item_ipv4()
2471 .dst_addr = RTE_BE32(0xffffffff), in mlx5_flow_validate_item_ipv4()
2578 .vtc_flow = RTE_BE32(0xffffffff), in mlx5_flow_validate_item_ipv6()
3002 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); in mlx5_flow_validate_item_gre_key()
3076 .key = RTE_BE32(UINT32_MAX), in mlx5_flow_validate_item_gre_option()
3079 .sequence = RTE_BE32(UINT32_MAX), in mlx5_flow_validate_item_gre_option()
3584 RTE_BE32(((const struct rte_ecpri_common_hdr) { in mlx5_flow_validate_item_ecpri()
H A Dmlx5_rx.c743 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) { in rxq_cq_to_mbuf()
H A Dmlx5_flow_meter.c1468 .cbs_cir = RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL), in mlx5_flow_meter_modify_state()
/dpdk/lib/ethdev/
H A Drte_flow.h959 .src_addr = RTE_BE32(0xffffffff),
960 .dst_addr = RTE_BE32(0xffffffff),
1111 .hdr.vx_vni = RTE_BE32(0xffffff00), /* (0xffffff << 8) */
1269 .teid = RTE_BE32(0xffffffff),
1286 .spi = RTE_BE32(0xffffffff),
1356 .spa = RTE_BE32(0xffffffff),
1358 .tpa = RTE_BE32(0xffffffff),
1652 .session_id = RTE_BE32(UINT32_MAX),
/dpdk/lib/eal/include/generic/
H A Drte_byteorder.h87 #define RTE_BE32(v) (rte_be32_t)(v) macro
94 #define RTE_BE32(v) (rte_be32_t)(RTE_STATIC_BSWAP32(v)) macro
/dpdk/drivers/crypto/mlx5/
H A Dmlx5_crypto.c302 return RTE_BE32(MLX5_BLOCK_SIZE_1MB << MLX5_BLOCK_SIZE_OFFSET); in mlx5_crypto_get_block_size()
304 return RTE_BE32(MLX5_BLOCK_SIZE_4096B << in mlx5_crypto_get_block_size()
307 return RTE_BE32(MLX5_BLOCK_SIZE_512B << MLX5_BLOCK_SIZE_OFFSET); in mlx5_crypto_get_block_size()
542 cseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR << in mlx5_crypto_qp_init()
545 ucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET); in mlx5_crypto_qp_init()
553 cseg->flags = RTE_BE32((MLX5_COMP_ALWAYS << in mlx5_crypto_qp_init()
/dpdk/drivers/net/mlx4/
H A Dmlx4_rxtx.c276 stamp ^= RTE_BE32(1u << MLX4_SQ_OWNER_BIT); in mlx4_txq_stamp_freed_wqe()
986 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT | in mlx4_tx_burst()
989 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT); in mlx4_tx_burst()
1004 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM); in mlx4_tx_burst()
1007 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM | in mlx4_tx_burst()
H A Dmlx4_flow.c608 .src_addr = RTE_BE32(0xffffffff),
609 .dst_addr = RTE_BE32(0xffffffff),
/dpdk/drivers/net/cxgbe/
H A Dcxgbe_flow.c993 .src_addr = RTE_BE32(0xffffffff),
994 .dst_addr = RTE_BE32(0xffffffff),
1010 .vtc_flow = RTE_BE32(0xff000000),
/dpdk/drivers/compress/mlx5/
H A Dmlx5_compress.c164 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS << in mlx5_compress_init_qp()
/dpdk/drivers/net/sfc/
H A Dsfc_mae.c2212 vtc_flow_be = RTE_BE32(RTE_IPV6_HDR_TC_MASK); in sfc_mae_rule_parse_item_ipv6()
3582 ipv6->vtc_flow = RTE_BE32(SFC_IPV6_VTC_FLOW_DEF); in sfc_mae_rule_parse_action_vxlan_encap()
3586 vxlan->vx_flags = RTE_BE32(SFC_VXLAN_FLAGS_DEF); in sfc_mae_rule_parse_action_vxlan_encap()
/dpdk/drivers/net/dpaa2/
H A Ddpaa2_flow.c113 .hdr.src_addr = RTE_BE32(0xffffffff),
114 .hdr.dst_addr = RTE_BE32(0xffffffff),
/dpdk/app/test-pmd/
H A Dcmdline_flow.c7445 RTE_BE32(0xfful << RTE_IPV6_HDR_TC_SHIFT); in parse_setup_vxlan_encap_data()
10676 static rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); in flow_item_default_mask()
H A Dcmdline.c13165 .vxlan_id = rte_cpu_to_be_32(res->vni) & RTE_BE32(0x00ffffff), in cmd_set_vxlan_parsed()
13365 .nvgre_tni = rte_cpu_to_be_32(res->tni) & RTE_BE32(0x00ffffff), in cmd_set_nvgre_parsed()