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Searched refs:BIT_ULL (Results 1 – 25 of 87) sorted by relevance

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/dpdk/drivers/net/hns3/
H A Dhns3_rss.c80 BIT_ULL(HNS3_RSS_FIELD_IPV4_EN_FRAG_IP_S) },
82 BIT_ULL(HNS3_RSS_FIELD_IPV4_EN_FRAG_IP_D) },
84 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_S) },
86 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_D) },
92 BIT_ULL(HNS3_RSS_FIELD_IPV4_UDP_EN_IP_S) },
94 BIT_ULL(HNS3_RSS_FIELD_IPV4_UDP_EN_IP_D) },
112 BIT_ULL(HNS3_RSS_FIELD_IPV6_FRAG_IP_S) },
114 BIT_ULL(HNS3_RSS_FIELD_IPV6_FRAG_IP_D) },
152 BIT_ULL(HNS3_RSS_FIELD_IPV4_TCP_EN_IP_D) |
156 BIT_ULL(HNS3_RSS_FIELD_IPV4_UDP_EN_IP_D) |
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/dpdk/drivers/net/ice/base/
H A Dice_flow.h21 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
22 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
24 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
25 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
27 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
28 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
76 (BIT_ULL(ICE_FLOW_FIELD_IDX_VXLAN_VNI))
79 (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
118 (BIT_ULL(ICE_FLOW_FIELD_IDX_PFCP_SEID))
132 (BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
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H A Dice_adminq_cmd.h1284 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1285 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1286 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1290 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1291 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1292 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1294 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1295 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1296 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1327 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
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H A Dice_type.h13 #define BIT_ULL(a) (1ULL << (a)) macro
117 #define ICE_DBG_INIT BIT_ULL(1)
120 #define ICE_DBG_LINK BIT_ULL(4)
121 #define ICE_DBG_PHY BIT_ULL(5)
122 #define ICE_DBG_QCTX BIT_ULL(6)
123 #define ICE_DBG_NVM BIT_ULL(7)
124 #define ICE_DBG_LAN BIT_ULL(8)
125 #define ICE_DBG_FLOW BIT_ULL(9)
126 #define ICE_DBG_DCB BIT_ULL(10)
128 #define ICE_DBG_FD BIT_ULL(12)
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/dpdk/drivers/common/cnxk/
H A Droc_model.h13 #define ROC_MODEL_CN96xx_A0 BIT_ULL(0)
14 #define ROC_MODEL_CN96xx_B0 BIT_ULL(1)
15 #define ROC_MODEL_CN96xx_C0 BIT_ULL(2)
16 #define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)
17 #define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)
18 #define ROC_MODEL_CNF95xxMM_A0 BIT_ULL(8)
19 #define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
20 #define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
28 #define ROC_ENV_HW BIT_ULL(61)
29 #define ROC_ENV_EMUL BIT_ULL(62)
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H A Droc_bphy_cgx_priv.h98 #define SCR0_ETH_EVT_STS_S_ACK BIT_ULL(0)
99 #define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
100 #define SCR0_ETH_EVT_STS_S_STAT BIT_ULL(2)
104 #define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9)
105 #define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
108 #define SCR0_ETH_LNK_STS_S_AN BIT_ULL(25)
124 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
128 #define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
129 #define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13)
H A Droc_nix_irq.c13 plt_write64(~(BIT_ULL(11) | BIT_ULL(24)), in nix_err_intr_enb_dis()
170 if (reg & BIT_ULL(42) /* OP_ERR */) { in nix_lf_q_irq_get_and_clear()
228 if (reg & BIT_ULL(44)) { in nix_lf_sq_debug_reg()
231 plt_write64(BIT_ULL(44), nix->base + off); in nix_lf_sq_debug_reg()
270 if (irq & BIT_ULL(NIX_RQINT_DROP)) in nix_lf_q_irq()
273 if (irq & BIT_ULL(NIX_RQINT_RED)) in nix_lf_q_irq()
282 if (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) in nix_lf_q_irq()
285 if (irq & BIT_ULL(NIX_CQERRINT_WR_FULL)) in nix_lf_q_irq()
288 if (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) in nix_lf_q_irq()
313 if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL) || in nix_lf_q_irq()
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H A Droc_nix.h77 ROC_NIX_BPF_GREEN_PKT_F_PASS = BIT_ULL(0),
78 ROC_NIX_BPF_GREEN_OCTS_F_PASS = BIT_ULL(1),
79 ROC_NIX_BPF_GREEN_PKT_F_DROP = BIT_ULL(2),
80 ROC_NIX_BPF_GREEN_OCTS_F_DROP = BIT_ULL(3),
81 ROC_NIX_BPF_YELLOW_PKT_F_PASS = BIT_ULL(4),
82 ROC_NIX_BPF_YELLOW_OCTS_F_PASS = BIT_ULL(5),
83 ROC_NIX_BPF_YELLOW_PKT_F_DROP = BIT_ULL(6),
85 ROC_NIX_BPF_RED_PKT_F_PASS = BIT_ULL(8),
86 ROC_NIX_BPF_RED_OCTS_F_PASS = BIT_ULL(9),
87 ROC_NIX_BPF_RED_PKT_F_DROP = BIT_ULL(10),
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H A Droc_npa.h8 #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1)
9 #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)
61 wdata |= BIT_ULL(63); /* DROP */ in roc_npa_aura_op_alloc()
75 reg |= BIT_ULL(63); /* FABS */ in roc_npa_aura_op_free()
92 if (reg & BIT_ULL(42) /* OP_ERR */) in roc_npa_aura_op_cnt_get()
101 uint64_t reg = count & (BIT_ULL(36) - 1); in roc_npa_aura_op_cnt_set()
104 reg |= BIT_ULL(43); /* CNT_ADD */ in roc_npa_aura_op_cnt_set()
124 if (reg & BIT_ULL(42) /* OP_ERR */) in roc_npa_aura_op_limit_get()
153 if (reg & BIT_ULL(42) /* OP_ERR */) in roc_npa_aura_op_available()
213 if (reg & BIT_ULL(48) /* OP_ERR */) in roc_npa_pool_op_performance_counter()
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H A Droc_npa_irq.c113 if (reg & BIT_ULL(42) /* OP_ERR */) { in npa_q_irq_get_and_clear()
161 if (irq & BIT_ULL(NPA_POOL_ERR_INT_OVFLS)) in npa_q_irq()
164 if (irq & BIT_ULL(NPA_POOL_ERR_INT_RANGE)) in npa_q_irq()
167 if (irq & BIT_ULL(NPA_POOL_ERR_INT_PERR)) in npa_q_irq()
180 if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_OVER)) in npa_q_irq()
183 if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_UNDER)) in npa_q_irq()
186 if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_FREE_UNDER)) in npa_q_irq()
189 if (irq & BIT_ULL(NPA_AURA_ERR_INT_POOL_DIS)) in npa_q_irq()
H A Droc_nix_priv.h39 #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)
40 #define NIX_TM_TL1_NO_SP BIT_ULL(1)
41 #define NIX_TM_TL1_ACCESS BIT_ULL(2)
42 #define NIX_TM_MARK_VLAN_DEI_EN BIT_ULL(3)
43 #define NIX_TM_MARK_IP_DSCP_EN BIT_ULL(4)
44 #define NIX_TM_MARK_IP_ECN_EN BIT_ULL(5)
86 #define NIX_TM_NODE_HWRES BIT_ULL(0)
87 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
/dpdk/drivers/net/ice/
H A Dice_generic_flow.h12 #define ICE_PROT_MAC BIT_ULL(1)
13 #define ICE_PROT_VLAN BIT_ULL(2)
14 #define ICE_PROT_IPV4 BIT_ULL(3)
15 #define ICE_PROT_IPV6 BIT_ULL(4)
16 #define ICE_PROT_TCP BIT_ULL(5)
17 #define ICE_PROT_UDP BIT_ULL(6)
18 #define ICE_PROT_SCTP BIT_ULL(7)
33 #define ICE_SMAC BIT_ULL(63)
34 #define ICE_DMAC BIT_ULL(62)
41 #define ICE_SPORT BIT_ULL(55)
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H A Dice_hash.c29 #define ICE_PHINT_VLAN BIT_ULL(0)
30 #define ICE_PHINT_PPPOE BIT_ULL(1)
31 #define ICE_PHINT_GTPU BIT_ULL(2)
32 #define ICE_PHINT_GTPU_EH BIT_ULL(3)
33 #define ICE_PHINT_GTPU_EH_DWN BIT_ULL(4)
34 #define ICE_PHINT_GTPU_EH_UP BIT_ULL(5)
35 #define ICE_PHINT_RAW BIT_ULL(6)
756 *hash_flds |= BIT_ULL(ICE_FLOW_FIELD_IDX_C_VLAN); in ice_refine_hash_cfg_l234()
758 *hash_flds |= BIT_ULL(ICE_FLOW_FIELD_IDX_S_VLAN); in ice_refine_hash_cfg_l234()
776 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID); in ice_refine_hash_cfg_l234()
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H A Dice_ethdev.h96 #define ICE_FLAG_RSS BIT_ULL(0)
97 #define ICE_FLAG_DCB BIT_ULL(1)
98 #define ICE_FLAG_VMDQ BIT_ULL(2)
99 #define ICE_FLAG_SRIOV BIT_ULL(3)
100 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
101 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
102 #define ICE_FLAG_FDIR BIT_ULL(6)
103 #define ICE_FLAG_VXLAN BIT_ULL(7)
104 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
105 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
/dpdk/drivers/net/i40e/base/
H A Di40e_type.h27 #ifndef BIT_ULL
28 #define BIT_ULL(a) (1ULL << (a)) macro
318 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
745 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
746 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
747 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
748 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
749 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
750 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
751 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
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H A Di40e_adminq_cmd.h1981 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1983 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1984 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1985 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1986 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1987 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1994 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1995 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1996 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1997 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
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/dpdk/drivers/common/cnxk/hw/
H A Dree.h14 #define REE_STATUS_PMI_EOJ_BIT BIT_ULL(14)
15 #define REE_STATUS_PMI_SOJ_BIT BIT_ULL(13)
16 #define REE_STATUS_MP_CNT_DET_BIT BIT_ULL(7)
17 #define REE_STATUS_MM_CNT_DET_BIT BIT_ULL(6)
18 #define REE_STATUS_ML_CNT_DET_BIT BIT_ULL(5)
19 #define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
20 #define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
59 #define REE_LF_ENA_ENA_MASK BIT_ULL(0)
H A Dtim.h21 #define TIM_AF_FLAGS_REG_ENA_TIM BIT_ULL(0)
22 #define TIM_AF_RINGX_CTL1_ENA BIT_ULL(47)
23 #define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50)
H A Dsso.h190 #define SSO_HWGRP_AW_CFG_RWEN BIT_ULL(0)
191 #define SSO_HWGRP_AW_CFG_LDWB BIT_ULL(1)
192 #define SSO_HWGRP_AW_CFG_LDT BIT_ULL(2)
193 #define SSO_HWGRP_AW_CFG_STT BIT_ULL(3)
194 #define SSO_HWGRP_AW_CFG_XAQ_BYP_DIS BIT_ULL(4)
196 #define SSO_HWGRP_AW_STS_TPTR_VLD BIT_ULL(8)
197 #define SSO_HWGRP_AW_STS_NPA_FETCH BIT_ULL(9)
/dpdk/drivers/raw/ifpga/base/
H A Dopae_spi.h32 #define CTRL_R BIT_ULL(9)
33 #define CTRL_W BIT_ULL(8)
36 #define READ_DATA_VALID BIT_ULL(32)
143 #define CONTROL_TYPE BIT_ULL(48)
147 #define CLOCK_PHASE BIT_ULL(15)
148 #define CLOCK_POLARITY BIT_ULL(14)
151 #define SHIFT_DIRECTION BIT_ULL(1)
152 #define SPI_TYPE BIT_ULL(0)
160 #define NIOS_SPI_VALID BIT_ULL(32)
/dpdk/drivers/net/i40e/
H A Di40e_hash.c23 #ifndef BIT_ULL
24 #define BIT_ULL(n) (1ULL << (n)) macro
154 BIT_ULL(RTE_FLOW_ITEM_TYPE_IPV6) | \
155 BIT_ULL(RTE_FLOW_ITEM_TYPE_VLAN))
158 BIT_ULL(RTE_FLOW_ITEM_TYPE_UDP) | \
160 BIT_ULL(RTE_FLOW_ITEM_TYPE_ESP) | \
162 BIT_ULL(RTE_FLOW_ITEM_TYPE_AH))
168 BIT_ULL(RTE_FLOW_ITEM_TYPE_GTPC))
171 BIT_ULL(RTE_FLOW_ITEM_TYPE_IPV6))
371 BIT_ULL(pattern->type))) in i40e_hash_get_pattern_type()
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/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_nsp_eth.c47 #define NSP_ETH_PORT_FEC_SUPP_RS BIT_ULL(61)
51 #define NSP_ETH_STATE_CONFIGURED BIT_ULL(0)
52 #define NSP_ETH_STATE_ENABLED BIT_ULL(1)
53 #define NSP_ETH_STATE_TX_ENABLED BIT_ULL(2)
54 #define NSP_ETH_STATE_RX_ENABLED BIT_ULL(3)
62 #define NSP_ETH_CTRL_CONFIGURED BIT_ULL(0)
63 #define NSP_ETH_CTRL_ENABLED BIT_ULL(1)
66 #define NSP_ETH_CTRL_SET_RATE BIT_ULL(4)
67 #define NSP_ETH_CTRL_SET_LANES BIT_ULL(5)
68 #define NSP_ETH_CTRL_SET_ANEG BIT_ULL(6)
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/dpdk/drivers/event/cnxk/
H A Dcn10k_eventdev.c127 req |= BIT_ULL(18); /* Grouped */ in cn10k_sso_hws_flush_events()
128 req |= BIT_ULL(16); /* WAIT */ in cn10k_sso_hws_flush_events()
149 } while (val & BIT_ULL(56)); in cn10k_sso_hws_flush_events()
185 if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) || in cn10k_sso_hws_reset()
191 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) | in cn10k_sso_hws_reset()
192 BIT_ULL(56) | BIT_ULL(54))); in cn10k_sso_hws_reset()
219 plt_write64(BIT_ULL(16) | 1, in cn10k_sso_hws_reset()
560 if (ptag & (BIT_ULL(62) | BIT_ULL(54)) || ws->swtag_req) in cn10k_sso_port_quiesce()
565 (BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54))); in cn10k_sso_port_quiesce()
581 BIT_ULL(63)) in cn10k_sso_port_quiesce()
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H A Dcn9k_eventdev.c140 req |= BIT_ULL(18); /* Grouped */ in cn9k_sso_hws_flush_events()
141 req |= BIT_ULL(16); /* WAIT */ in cn9k_sso_hws_flush_events()
172 } while (val & BIT_ULL(56)); in cn9k_sso_hws_flush_events()
208 if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) || in cn9k_sso_hws_reset()
215 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) | in cn9k_sso_hws_reset()
216 BIT_ULL(56))); in cn9k_sso_hws_reset()
707 dws->gw_wdata = BIT_ULL(16); in cn9k_sso_init_hws_mem()
728 ws->gw_wdata = BIT_ULL(16); in cn9k_sso_init_hws_mem()
835 if (ptag & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) || in cn9k_sso_port_quiesce()
842 } while (ptag & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) | in cn9k_sso_port_quiesce()
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/dpdk/drivers/common/iavf/
H A Diavf_type.h24 #define BIT_ULL(a) (1ULL << (a)) macro
349 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
350 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
351 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
352 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
353 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
633 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
863 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
895 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
900 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
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