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Searched refs:AXGMAC_SET_BITS (Results 1 – 3 of 3) sorted by relevance

/dpdk/drivers/net/axgbe/
H A Daxgbe_dev.c73 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); in axgbe_write_ext_mii_regs()
74 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); in axgbe_write_ext_mii_regs()
79 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); in axgbe_write_ext_mii_regs()
80 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); in axgbe_write_ext_mii_regs()
101 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); in axgbe_read_ext_mii_regs()
102 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); in axgbe_read_ext_mii_regs()
106 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); in axgbe_read_ext_mii_regs()
107 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); in axgbe_read_ext_mii_regs()
279 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); in axgbe_disable_tx_flow_control()
317 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); in axgbe_enable_tx_flow_control()
[all …]
H A Daxgbe_ethdev.c598 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); in axgbe_dev_rss_hash_update()
1663 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); in axgbe_timesync_enable()
1666 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); in axgbe_timesync_enable()
1669 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); in axgbe_timesync_enable()
1674 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); in axgbe_timesync_enable()
1675 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); in axgbe_timesync_enable()
1677 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); in axgbe_timesync_enable()
1680 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); in axgbe_timesync_enable()
1726 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); in axgbe_timesync_disable()
1730 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); in axgbe_timesync_disable()
[all …]
H A Daxgbe_common.h1462 #define AXGMAC_SET_BITS(_var, _prefix, _field, _val) \ macro