Lines Matching refs:AXGMAC_SET_BITS
73 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); in axgbe_write_ext_mii_regs()
74 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); in axgbe_write_ext_mii_regs()
78 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); in axgbe_write_ext_mii_regs()
79 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); in axgbe_write_ext_mii_regs()
80 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); in axgbe_write_ext_mii_regs()
101 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); in axgbe_read_ext_mii_regs()
102 AXGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); in axgbe_read_ext_mii_regs()
106 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); in axgbe_read_ext_mii_regs()
107 AXGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); in axgbe_read_ext_mii_regs()
279 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); in axgbe_disable_tx_flow_control()
317 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); in axgbe_enable_tx_flow_control()
319 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); in axgbe_enable_tx_flow_control()
640 AXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0x3); in axgbe_config_dma_cache()
644 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0x3); in axgbe_config_dma_cache()
645 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0x3); in axgbe_config_dma_cache()
646 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, 0x1); in axgbe_config_dma_cache()
647 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0x3); in axgbe_config_dma_cache()
648 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, 0x1); in axgbe_config_dma_cache()
649 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0x3); in axgbe_config_dma_cache()
650 AXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDD, 0x1); in axgbe_config_dma_cache()
654 AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWD, 0x1); in axgbe_config_dma_cache()
655 AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0x3); in axgbe_config_dma_cache()
656 AXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0x3); in axgbe_config_dma_cache()
844 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); in axgbe_rss_options()
846 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); in axgbe_rss_options()
848 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); in axgbe_rss_options()
862 AXGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, in axgbe_config_rss()
897 AXGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 0); in axgbe_enable_dma_interrupts()
898 AXGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); in axgbe_enable_dma_interrupts()
899 AXGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); in axgbe_enable_dma_interrupts()
907 AXGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); in axgbe_enable_dma_interrupts()
1219 AXGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); in axgbe_set_mac_addn_addr()