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Searched defs:reg (Results 1 – 25 of 212) sorted by relevance

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/dpdk/lib/bpf/
H A Dbpf_exec.c17 #define BPF_JMP_CND_REG(reg, ins, op, type) \ argument
22 #define BPF_JMP_CND_IMM(reg, ins, op, type) \ argument
27 #define BPF_NEG_ALU(reg, ins, type) \ argument
30 #define EBPF_MOV_ALU_REG(reg, ins, type) \ argument
33 #define BPF_OP_ALU_REG(reg, ins, op, type) \ argument
37 #define EBPF_MOV_ALU_IMM(reg, ins, type) \ argument
54 #define BPF_LD_REG(reg, ins, type) \ argument
58 #define BPF_ST_IMM(reg, ins, type) \ argument
62 #define BPF_ST_REG(reg, ins, type) \ argument
66 #define BPF_ST_XADD_REG(reg, ins, tp) \ argument
[all …]
/dpdk/drivers/net/igc/base/
H A Digc_osdep.h81 #define IGC_PCI_REG(reg) rte_read32(reg) argument
83 #define IGC_PCI_REG16(reg) rte_read16(reg) argument
85 #define IGC_PCI_REG_WRITE(reg, value) \ argument
91 #define IGC_PCI_REG_WRITE16(reg, value) \ argument
94 #define IGC_PCI_REG_ADDR(hw, reg) \ argument
100 #define IGC_PCI_REG_FLASH_ADDR(hw, reg) \ argument
115 #define IGC_READ_REG(hw, reg) \ argument
118 #define IGC_READ_REG_LE_VALUE(hw, reg) \ argument
121 #define IGC_WRITE_REG(hw, reg, value) \ argument
151 #define IGC_READ_FLASH_REG(hw, reg) \ argument
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H A Digc_osdep.c14 igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) in igc_write_pci_cfg()
22 igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) in igc_read_pci_cfg()
45 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) in igc_read_pcie_cap_reg()
57 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) in igc_write_pcie_cap_reg()
/dpdk/drivers/net/e1000/base/
H A De1000_osdep.h71 #define E1000_PCI_REG(reg) rte_read32(reg) argument
73 #define E1000_PCI_REG16(reg) rte_read16(reg) argument
75 #define E1000_PCI_REG_WRITE(reg, value) \ argument
81 #define E1000_PCI_REG_WRITE16(reg, value) \ argument
84 #define E1000_PCI_REG_ADDR(hw, reg) \ argument
90 #define E1000_PCI_REG_FLASH_ADDR(hw, reg) \ argument
117 #define E1000_READ_REG(hw, reg) \ argument
120 #define E1000_WRITE_REG(hw, reg, value) \ argument
143 #define E1000_WRITE_REG_IO(hw, reg, value) \ argument
150 #define E1000_READ_FLASH_REG(hw, reg) \ argument
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H A De1000_osdep.c15 e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) in e1000_write_pci_cfg()
21 e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) in e1000_read_pci_cfg()
42 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) in e1000_read_pcie_cap_reg()
51 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) in e1000_write_pcie_cap_reg()
/dpdk/drivers/vdpa/ifc/base/
H A Difcvf_osdep.h22 #define IFCVF_READ_REG8(reg) rte_read8(reg) argument
23 #define IFCVF_WRITE_REG8(val, reg) rte_write8((val), (reg)) argument
24 #define IFCVF_READ_REG16(reg) rte_read16(reg) argument
25 #define IFCVF_WRITE_REG16(val, reg) rte_write16((val), (reg)) argument
26 #define IFCVF_READ_REG32(reg) rte_read32(reg) argument
27 #define IFCVF_WRITE_REG32(val, reg) rte_write32((val), (reg)) argument
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_osdep.h104 #define IXGBE_PCI_REG(reg) rte_read32(reg) argument
111 #define IXGBE_PCI_REG_WRITE(reg, value) \ argument
114 #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \ argument
117 #define IXGBE_PCI_REG_WC_WRITE(reg, value) \ argument
120 #define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value) \ argument
123 #define IXGBE_PCI_REG_ADDR(hw, reg) \ argument
126 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \ argument
130 #define IXGBE_READ_PCIE_WORD(hw, reg) 0 argument
135 #define IXGBE_READ_REG(hw, reg) \ argument
138 #define IXGBE_WRITE_REG(hw, reg, value) \ argument
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H A Dixgbe_dcb_82599.c95 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
156 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82599() local
206 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82599() local
266 u32 i, j, fcrtl, reg; in ixgbe_dcb_config_pfc_82599() local
354 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82599() local
480 u32 reg; in ixgbe_dcb_config_82599() local
H A Dixgbe_dcb_82598.c85 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
144 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82598() local
191 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82598() local
234 u32 fcrtl, reg; in ixgbe_dcb_config_pfc_82598() local
286 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82598() local
H A Dixgbe_x550.c152 u8 reg; in ixgbe_reset_cs4227() local
516 u16 reg, u16 *val) in ixgbe_read_i2c_combined_generic()
532 u16 reg, u16 *val) in ixgbe_read_i2c_combined_generic_unlocked()
563 u8 addr, u16 reg, u16 val) in ixgbe_write_i2c_combined_generic_unlocked()
855 u32 reg, high_pri_tc; in ixgbe_dmac_config_X550() local
958 u32 reg; in ixgbe_dmac_update_tcs_X550() local
1329 u32 reg; in ixgbe_disable_mdd_X550() local
1352 u32 reg; in ixgbe_enable_mdd_X550() local
1939 u16 reg; in ixgbe_get_lasi_ext_t_x550em() local
2026 u16 reg; in ixgbe_enable_lasi_ext_t_x550em() local
[all …]
/dpdk/drivers/event/dlb2/pf/base/
H A Ddlb2_osdep.h27 #define DLB2_PCI_REG_WRITE(reg, value) rte_write32(value, (void *)reg) argument
30 #define DLB2_CSR_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->csr_kva + (reg))) argument
31 #define DLB2_CSR_RD(hw, reg) \ argument
33 #define DLB2_CSR_WR(hw, reg, value) \ argument
37 #define DLB2_FUNC_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->func_kva + (reg))) argument
38 #define DLB2_FUNC_RD(hw, reg) \ argument
40 #define DLB2_FUNC_WR(hw, reg, value) \ argument
/dpdk/drivers/net/ionic/
H A Dionic_osdep.h42 #define ioread8(reg) rte_read8(reg) argument
43 #define ioread32(reg) rte_read32(rte_le_to_cpu_32(reg)) argument
44 #define iowrite8(value, reg) rte_write8(value, reg) argument
45 #define iowrite32(value, reg) rte_write32(rte_cpu_to_le_32(value), reg) argument
/dpdk/drivers/net/i40e/base/
H A Di40e_osdep.h138 #define I40E_PCI_REG(reg) rte_read32(reg) argument
139 #define I40E_PCI_REG_ADDR(a, reg) \ argument
146 #define I40E_PCI_REG64(reg) rte_read64(reg) argument
147 #define I40E_PCI_REG64_ADDR(a, reg) \ argument
154 #define I40E_PCI_REG_WRITE(reg, value) \ argument
156 #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \ argument
159 #define I40E_PCI_REG_WC_WRITE(reg, value) \ argument
161 #define I40E_PCI_REG_WC_WRITE_RELAXED(reg, value) \ argument
167 #define I40E_WRITE_REG(hw, reg, value) \ argument
172 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) argument
[all …]
H A Di40e_diag.c33 u32 reg, u32 mask) in i40e_diag_reg_pattern_test()
83 u32 reg, mask; in i40e_diag_reg_test() local
/dpdk/drivers/net/axgbe/
H A Daxgbe_mdio.c12 int reg; in axgbe_an37_clear_interrupts() local
21 int reg; in axgbe_an37_disable_interrupts() local
34 unsigned int reg; in axgbe_an37_enable_interrupts() local
221 unsigned int reg; in axgbe_an37_set() local
250 unsigned int reg; in axgbe_an73_set() local
334 unsigned int ad_reg, lp_reg, reg; in axgbe_an73_tx_training() local
389 unsigned int reg, ad_reg, lp_reg; in axgbe_an73_rx_bpa() local
668 unsigned int reg = 0; in axgbe_an37_isr() local
715 unsigned int reg = 0; in axgbe_an37_init() local
756 unsigned int advertising, reg; in axgbe_an73_init() local
[all …]
/dpdk/drivers/net/fm10k/base/
H A Dfm10k_osdep.h58 #define FM10K_WRITE_REG(hw, reg, val) \ argument
61 #define FM10K_READ_REG(hw, reg) rte_read32(((hw)->hw_addr + (reg))) argument
65 #define FM10K_PCI_REG(reg) rte_read32(reg) argument
67 #define FM10K_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) argument
70 #define FM10K_READ_PCI_WORD(hw, reg) 0 argument
72 #define FM10K_WRITE_MBX(hw, reg, value) FM10K_WRITE_REG(hw, reg, value) argument
73 #define FM10K_READ_MBX(hw, reg) FM10K_READ_REG(hw, reg) argument
/dpdk/drivers/raw/ifpga/base/
H A Dopae_spi.c8 static int nios_spi_indirect_read(struct altera_spi_device *dev, u32 reg, in nios_spi_indirect_read()
27 static int nios_spi_indirect_write(struct altera_spi_device *dev, u32 reg, in nios_spi_indirect_write()
47 static int spi_indirect_write(struct altera_spi_device *dev, u32 reg, in spi_indirect_write()
60 static int spi_indirect_read(struct altera_spi_device *dev, u32 reg, in spi_indirect_read()
81 int spi_reg_write(struct altera_spi_device *dev, u32 reg, in spi_reg_write()
87 int spi_reg_read(struct altera_spi_device *dev, u32 reg, in spi_reg_read()
/dpdk/drivers/net/vmxnet3/
H A Dvmxnet3_ethdev.h136 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg)) argument
137 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32)) argument
141 #define VMXNET3_PCI_REG(reg) rte_read32(reg) argument
149 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) argument
151 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \ argument
153 #define VMXNET3_READ_BAR0_REG(hw, reg) \ argument
155 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \ argument
158 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \ argument
160 #define VMXNET3_READ_BAR1_REG(hw, reg) \ argument
162 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \ argument
/dpdk/drivers/common/iavf/
H A Diavf_osdep.h119 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg)) argument
120 #define rd32(a, reg) readl((a)->hw_addr + (reg)) argument
121 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg)) argument
122 #define rd64(a, reg) readq((a)->hw_addr + (reg)) argument
132 #define IAVF_PCI_REG_WRITE(reg, value) writel(value, reg) argument
133 #define IAVF_PCI_REG_WRITE_RELAXED(reg, value) writel_relaxed(value, reg) argument
135 #define IAVF_PCI_REG_WC_WRITE(reg, value) \ argument
137 #define IAVF_PCI_REG_WC_WRITE_RELAXED(reg, value) \ argument
140 #define IAVF_READ_REG(hw, reg) rd32(hw, reg) argument
141 #define IAVF_WRITE_REG(hw, reg, value) wr32(hw, reg, value) argument
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_dcb_hw.c25 u32 reg = 0; in txgbe_dcb_config_rx_arbiter_raptor() local
87 u32 reg, max_credits; in txgbe_dcb_config_tx_desc_arbiter_raptor() local
135 u32 reg; in txgbe_dcb_config_tx_data_arbiter_raptor() local
194 u32 i, j, fcrtl, reg; in txgbe_dcb_config_pfc_raptor() local
/dpdk/drivers/common/cnxk/
H A Droc_nix_debug.c9 #define NIX_REG_INFO(reg) \ argument
118 uint64_t reg; in nix_lf_gen_reg_dump() local
140 uint64_t reg; in nix_lf_stat_reg_dump() local
174 uint64_t reg; in nix_lf_int_reg_dump() local
866 uint64_t *reg, char regstr[][NIX_REG_NAME_SZ]) in nix_tm_reg_dump_prep()
1036 uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2]; in nix_tm_dump_lvl() local
H A Droc_npa.h71 uint64_t reg = roc_npa_aura_handle_to_aura(aura_handle); in roc_npa_aura_op_free() local
85 uint64_t reg; in roc_npa_aura_op_cnt_get() local
101 uint64_t reg = count & (BIT_ULL(36) - 1); in roc_npa_aura_op_cnt_set() local
117 uint64_t reg; in roc_npa_aura_op_limit_get() local
133 uint64_t reg = limit & ROC_AURA_OP_LIMIT_MASK; in roc_npa_aura_op_limit_set() local
145 uint64_t reg; in roc_npa_aura_op_available() local
193 uint64_t reg; in roc_npa_pool_op_performance_counter() local
/dpdk/drivers/net/atlantic/
H A Datl_hw_regs.c34 u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) in aq_hw_read_reg()
39 void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) in aq_hw_write_reg()
/dpdk/lib/eal/x86/
H A Drte_cpuflags.c20 uint32_t reg; /**< cpuid register */ member
26 #define FEAT_DEF(name, leaf, subleaf, reg, bit) \ argument
/dpdk/lib/eal/ppc/
H A Drte_cpuflags.c29 uint32_t reg; member
35 #define FEAT_DEF(name, reg, bit) \ argument

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