| /llvm-project-15.0.7/llvm/include/llvm/Transforms/Instrumentation/ |
| H A D | AddressSanitizerCommon.h | 28 bool IsWrite; variable
38 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() function
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| H A D | AddressSanitizer.h | 58 const bool IsWrite; member
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| /llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemProfiler.cpp | 157 bool IsWrite; member
427 Type *AccessTy, bool IsWrite) { in instrumentMaskedLoadOrStore()
488 uint32_t TypeSize, bool IsWrite) { in instrumentAddress()
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| H A D | AddressSanitizer.cpp | 606 ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel, in ASanAccessInfo()
1300 bool IsWrite = CI->getIntrinsicID() == Intrinsic::masked_store; in getInterestingMemoryOperands() local
1388 uint32_t TypeSize, bool IsWrite, in doInstrumentAddress()
1407 bool IsWrite, Value *SizeArgument, in instrumentMaskedLoadOrStore()
1497 Value *Addr, bool IsWrite, in generateCrashCode()
1544 uint32_t TypeSize, bool IsWrite, Value *SizeArgument) { in instrumentAMDGPUAddress()
1567 uint32_t TypeSize, bool IsWrite, in instrumentAddress()
1647 bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) { in instrumentUnusualSizeOrAlignment()
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| H A D | ThreadSanitizer.cpp | 432 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
600 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
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| H A D | HWAddressSanitizer.cpp | 813 int64_t HWAddressSanitizer::getAccessInfo(bool IsWrite, in getAccessInfo()
823 void HWAddressSanitizer::instrumentMemAccessOutline(Value *Ptr, bool IsWrite, in instrumentMemAccessOutline()
838 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline()
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| /llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/ |
| H A D | tsan_shadow.h | 168 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | LoopAccessAnalysis.h | 249 ArrayRef<unsigned> getOrderForAccess(Value *Ptr, bool IsWrite) const { in getOrderForAccess()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | LoopAccessAnalysis.cpp | 977 bool IsWrite = Access.getInt(); in createCheckForAccess() local
1020 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
1191 bool IsWrite = AC.first.getInt(); in processMemAccesses() local
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| /llvm-project-15.0.7/llvm/lib/Transforms/IPO/ |
| H A D | FunctionAttrs.cpp | 676 bool IsWrite = false; in determinePointerAccessAttrs() local
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4428 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in lowerPREFETCH() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3660 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in LowerPREFETCH() local
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