| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 389 Register FirstReg; in CreateRegs() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1393 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1395 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1397 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3365 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3382 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3436 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3501 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4342 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5284 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5331 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 494 unsigned FirstReg = 0; in ScanInstruction() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord()
2420 Register FirstReg, SecondReg; in RescheduleOps() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1656 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3915 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
4006 unsigned FirstReg; in tryParseVectorList() local
6915 unsigned FirstReg; in tryParseGPRSeqPair() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4350 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4403 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4550 unsigned FirstReg = 0; in HandleByVal() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2532 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1639 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
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| H A D | PPCISelLowering.cpp | 6780 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 4773 unsigned FirstReg = Reg; in parseVectorList() local
|