| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 100 const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, in changeFCMPPredToAArch64CC()
154 const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, in changeVectorFCMPPredToAArch64CC()
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| H A D | AArch64InstructionSelector.cpp | 1277 AArch64CC::CondCode &CondCode, in changeFPCCToORAArch64CC()
1334 AArch64CC::CondCode &CondCode, in changeFPCCToANDAArch64CC()
5027 AArch64CC::CondCode CondCode; in tryOptSelect() local
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 30 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/MCTargetDesc/ |
| H A D | ARCInfo.h | 24 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiCondCode.h | 10 enum CondCode { enum
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| H A D | LanaiInstrInfo.cpp | 520 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.h | 34 enum CondCode { enum
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| H A D | M68kISelLowering.cpp | 2052 unsigned CondCode = in LowerSELECT() local
2193 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); in LowerSELECT() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsInstPrinter.h | 32 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, in insertTrackingCode()
247 AArch64CC::CondCode CondCode; in instrumentControlFlow() local
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| H A D | AArch64ISelLowering.cpp | 2362 unsigned CondCode = MI.getOperand(3).getImm(); in EmitF128CSEL() local
2718 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC()
2781 AArch64CC::CondCode &CondCode, in changeFPCCToANDAArch64CC()
2811 AArch64CC::CondCode &CondCode, in changeVectorFPCCToAArch64CC()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VE.h | 40 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 37 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 1077 LPCC::CondCode CondCode = in splitMnemonic() local
1097 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic() local
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 928 for (int CondCode : CondCodes) in generateInstructionVariants() local
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 336 unsigned CondCode; in parseJccInstruction() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 254 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 537 static unsigned getPTXCmpMode(const CondCodeSDNode &CondCode, bool FTZ) { in getPTXCmpMode()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 80 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1424 enum CondCode { enum
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| /llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 859 VECC::CondCode CondCode = in parseCC() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 2025 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC()
4796 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in getARMCmp() local
5145 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in checkVSELConstraints()
5482 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in LowerSELECT_CC() local
5499 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
5644 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); in OptimizeVFPBrcond() local
5678 ARMCC::CondCodes CondCode = in LowerBRCOND() local
5731 ARMCC::CondCodes CondCode = in LowerBR_CC() local
5757 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
10306 ARMCC::CondCodes CondCode, CondCode2; in LowerFSETCC() local
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| H A D | ARMBaseInstrInfo.cpp | 2385 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2876 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5779 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
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