Lines Matching refs:where
17 cap_tph(struct device *d, int where) in cap_tph() argument
24 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) in cap_tph()
27 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); in cap_tph()
59 cap_ltr(struct device *d, int where) in cap_ltr() argument
67 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) in cap_ltr()
70 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); in cap_ltr()
75 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); in cap_ltr()
82 cap_sec(struct device *d, int where) in cap_sec() argument
90 if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12)) in cap_sec()
93 ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3); in cap_sec()
98 lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR); in cap_sec()
113 cap_dsn(struct device *d, int where) in cap_dsn() argument
116 if (!config_fetch(d, where + 4, 8)) in cap_dsn()
118 t1 = get_conf_long(d, where + 4); in cap_dsn()
119 t2 = get_conf_long(d, where + 8); in cap_dsn()
126 cap_aer(struct device *d, int where, int type) in cap_aer() argument
135 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40)) in cap_aer()
138 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); in cap_aer()
151 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK); in cap_aer()
164 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER); in cap_aer()
177 l = get_conf_long(d, where + PCI_ERR_COR_STATUS); in cap_aer()
183 l = get_conf_long(d, where + PCI_ERR_COR_MASK); in cap_aer()
189 l = get_conf_long(d, where + PCI_ERR_CAP); in cap_aer()
197 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG); in cap_aer()
198 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4); in cap_aer()
199 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); in cap_aer()
200 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); in cap_aer()
205 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12)) in cap_aer()
208 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); in cap_aer()
214 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); in cap_aer()
226 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC); in cap_aer()
229 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC); in cap_aer()
234 static void cap_dpc(struct device *d, int where) in cap_dpc() argument
242 if (!config_fetch(d, where + PCI_DPC_CAP, 8)) in cap_dpc()
245 l = get_conf_word(d, where + PCI_DPC_CAP); in cap_dpc()
250 l = get_conf_word(d, where + PCI_DPC_CTL); in cap_dpc()
256 l = get_conf_word(d, where + PCI_DPC_STATUS); in cap_dpc()
261 l = get_conf_word(d, where + PCI_DPC_SOURCE); in cap_dpc()
266 cap_acs(struct device *d, int where) in cap_acs() argument
274 if (!config_fetch(d, where + PCI_ACS_CAP, 4)) in cap_acs()
277 w = get_conf_word(d, where + PCI_ACS_CAP); in cap_acs()
283 w = get_conf_word(d, where + PCI_ACS_CTRL); in cap_acs()
292 cap_ari(struct device *d, int where) in cap_ari() argument
300 if (!config_fetch(d, where + PCI_ARI_CAP, 4)) in cap_ari()
303 w = get_conf_word(d, where + PCI_ARI_CAP); in cap_ari()
307 w = get_conf_word(d, where + PCI_ARI_CTRL); in cap_ari()
314 cap_ats(struct device *d, int where) in cap_ats() argument
322 if (!config_fetch(d, where + PCI_ATS_CAP, 4)) in cap_ats()
325 w = get_conf_word(d, where + PCI_ATS_CAP); in cap_ats()
327 w = get_conf_word(d, where + PCI_ATS_CTRL); in cap_ats()
333 cap_pri(struct device *d, int where) in cap_pri() argument
342 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) in cap_pri()
345 w = get_conf_word(d, where + PCI_PRI_CTRL); in cap_pri()
348 w = get_conf_word(d, where + PCI_PRI_STATUS); in cap_pri()
352 l = get_conf_long(d, where + PCI_PRI_MAX_REQ); in cap_pri()
354 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); in cap_pri()
359 cap_pasid(struct device *d, int where) in cap_pasid() argument
367 if (!config_fetch(d, where + PCI_PASID_CAP, 4)) in cap_pasid()
370 w = get_conf_word(d, where + PCI_PASID_CAP); in cap_pasid()
374 w = get_conf_word(d, where + PCI_PASID_CTRL); in cap_pasid()
381 cap_sriov(struct device *d, int where) in cap_sriov() argument
392 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c)) in cap_sriov()
395 l = get_conf_long(d, where + PCI_IOV_CAP); in cap_sriov()
398 w = get_conf_word(d, where + PCI_IOV_CTRL); in cap_sriov()
403 w = get_conf_word(d, where + PCI_IOV_STATUS); in cap_sriov()
405 w = get_conf_word(d, where + PCI_IOV_INITIALVF); in cap_sriov()
407 w = get_conf_word(d, where + PCI_IOV_TOTALVF); in cap_sriov()
409 w = get_conf_word(d, where + PCI_IOV_NUMVF); in cap_sriov()
411 b = get_conf_byte(d, where + PCI_IOV_FDL); in cap_sriov()
413 w = get_conf_word(d, where + PCI_IOV_OFFSET); in cap_sriov()
415 w = get_conf_word(d, where + PCI_IOV_STRIDE); in cap_sriov()
417 w = get_conf_word(d, where + PCI_IOV_DID); in cap_sriov()
419 l = get_conf_long(d, where + PCI_IOV_SUPPS); in cap_sriov()
421 l = get_conf_long(d, where + PCI_IOV_SYSPS); in cap_sriov()
429 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i); in cap_sriov()
440 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4)); in cap_sriov()
449 l = get_conf_long(d, where + PCI_IOV_MSAO); in cap_sriov()
455 cap_multicast(struct device *d, int where, int type) in cap_multicast() argument
465 if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30)) in cap_multicast()
468 w = get_conf_word(d, where + PCI_MCAST_CAP); in cap_multicast()
476 w = get_conf_word(d, where + PCI_MCAST_CTRL); in cap_multicast()
479 bar = get_conf_long(d, where + PCI_MCAST_BAR); in cap_multicast()
480 l = get_conf_long(d, where + PCI_MCAST_BAR + 4); in cap_multicast()
484 rcv = get_conf_long(d, where + PCI_MCAST_RCV); in cap_multicast()
485 l = get_conf_long(d, where + PCI_MCAST_RCV + 4); in cap_multicast()
488 block = get_conf_long(d, where + PCI_MCAST_BLOCK); in cap_multicast()
489 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4); in cap_multicast()
492 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS); in cap_multicast()
493 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4); in cap_multicast()
499 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR); in cap_multicast()
500 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4); in cap_multicast()
511 cap_vc(struct device *d, int where) in cap_vc() argument
527 if (!config_fetch(d, where + 4, 0x1c - 4)) in cap_vc()
530 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1); in cap_vc()
531 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2); in cap_vc()
532 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL); in cap_vc()
533 status = get_conf_word(d, where + PCI_VC_PORT_STATUS); in cap_vc()
552 arb_table_pos = where + 16*arb_table_pos; in cap_vc()
558 int pos = where + PCI_VC_RES_CAP + 12*i; in cap_vc()
600 cap_rclink(struct device *d, int where) in cap_rclink() argument
612 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4)) in cap_rclink()
615 esd = get_conf_long(d, where + PCI_RCLINK_ESD); in cap_rclink()
624 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE; in cap_rclink()
662 cap_rcec(struct device *d, int where) in cap_rcec() argument
668 if (!config_fetch(d, where, 12)) in cap_rcec()
671 u32 hdr = get_conf_long(d, where); in cap_rcec()
673 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); in cap_rcec()
706 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); in cap_rcec()
717 cap_lmr(struct device *d, int where) in cap_lmr() argument
724 if (!config_fetch(d, where, 8)) in cap_lmr()
727 u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS); in cap_lmr()
728 u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS); in cap_lmr()
737 cap_phy_16gt(struct device *d, int where) in cap_phy_16gt() argument
744 if (!config_fetch(d, where + PCI_16GT_CAP, 0x18)) { in cap_phy_16gt()
749 u32 status = get_conf_long(d, where + PCI_16GT_STATUS); in cap_phy_16gt()
760 cap_phy_32gt(struct device *d, int where) in cap_phy_32gt() argument
780 if (!config_fetch(d, where + PCI_32GT_CAP, 0x1C)) { in cap_phy_32gt()
785 u32 cap = get_conf_long(d, where + PCI_32GT_CAP); in cap_phy_32gt()
786 u32 ctl = get_conf_long(d, where + PCI_32GT_CTL); in cap_phy_32gt()
787 u32 status = get_conf_long(d, where + PCI_32GT_STATUS); in cap_phy_32gt()
819 cap_phy_64gt(struct device *d, int where) in cap_phy_64gt() argument
826 if (!config_fetch(d, where + PCI_64GT_CAP, 0x0C)) { in cap_phy_64gt()
831 u32 status = get_conf_long(d, where + PCI_64GT_STATUS); in cap_phy_64gt()
866 dvsec_cxl_device(struct device *d, int rev, int where, int len) in dvsec_cxl_device() argument
878 w = get_conf_word(d, where + PCI_CXL_DEV_CAP); in dvsec_cxl_device()
883 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL); in dvsec_cxl_device()
889 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS); in dvsec_cxl_device()
892 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2); in dvsec_cxl_device()
902 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2); in dvsec_cxl_device()
906 w = get_conf_word(d, where + PCI_CXL_DEV_CAP2); in dvsec_cxl_device()
926 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32; in dvsec_cxl_device()
927 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO); in dvsec_cxl_device()
928 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32; in dvsec_cxl_device()
929 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO); in dvsec_cxl_device()
932 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32; in dvsec_cxl_device()
933 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO); in dvsec_cxl_device()
934 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32; in dvsec_cxl_device()
935 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO); in dvsec_cxl_device()
941 w = get_conf_word(d, where + PCI_CXL_DEV_CAP3); in dvsec_cxl_device()
955 dvsec_cxl_port(struct device *d, int where, int len) in dvsec_cxl_port() argument
963 w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS); in dvsec_cxl_port()
966 w = get_conf_word(d, where + PCI_CXL_PORT_CTRL); in dvsec_cxl_port()
972 b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE); in dvsec_cxl_port()
973 b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT); in dvsec_cxl_port()
975 m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE); in dvsec_cxl_port()
976 m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT); in dvsec_cxl_port()
981 dvsec_cxl_register_locator(struct device *d, int where, int len) in dvsec_cxl_register_locator() argument
993 int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i; in dvsec_cxl_register_locator()
994 if (pos + 7 >= where + len) in dvsec_cxl_register_locator()
1020 dvsec_cxl_gpf_device(struct device *d, int where) in dvsec_cxl_gpf_device() argument
1026 w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR); in dvsec_cxl_gpf_device()
1057 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW); in dvsec_cxl_gpf_device()
1062 dvsec_cxl_gpf_port(struct device *d, int where) in dvsec_cxl_gpf_port() argument
1067 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL); in dvsec_cxl_gpf_port()
1098 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL); in dvsec_cxl_gpf_port()
1131 dvsec_cxl_flex_bus(struct device *d, int where, int rev, int len) in dvsec_cxl_flex_bus() argument
1155 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP); in dvsec_cxl_flex_bus()
1165 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL); in dvsec_cxl_flex_bus()
1177 w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS); in dvsec_cxl_flex_bus()
1192 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA); in dvsec_cxl_flex_bus()
1202 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2); in dvsec_cxl_flex_bus()
1205 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2); in dvsec_cxl_flex_bus()
1208 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2); in dvsec_cxl_flex_bus()
1219 dvsec_cxl_mld(struct device *d, int where) in dvsec_cxl_mld() argument
1223 w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD); in dvsec_cxl_mld()
1231 dvsec_cxl_function_map(struct device *d, int where) in dvsec_cxl_function_map() argument
1235 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0))); in dvsec_cxl_function_map()
1238 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1))); in dvsec_cxl_function_map()
1241 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2))); in dvsec_cxl_function_map()
1244 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3))); in dvsec_cxl_function_map()
1247 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4))); in dvsec_cxl_function_map()
1250 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5))); in dvsec_cxl_function_map()
1253 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6))); in dvsec_cxl_function_map()
1256 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7))); in dvsec_cxl_function_map()
1260 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len) in cap_dvsec_cxl() argument
1266 if (!config_fetch(d, where, len)) in cap_dvsec_cxl()
1273 dvsec_cxl_device(d, rev, where, len); in cap_dvsec_cxl()
1277 dvsec_cxl_function_map(d, where); in cap_dvsec_cxl()
1281 dvsec_cxl_port(d, where, len); in cap_dvsec_cxl()
1285 dvsec_cxl_gpf_port(d, where); in cap_dvsec_cxl()
1289 dvsec_cxl_gpf_device(d, where); in cap_dvsec_cxl()
1293 dvsec_cxl_flex_bus(d, where, rev, len); in cap_dvsec_cxl()
1297 dvsec_cxl_register_locator(d, where, len); in cap_dvsec_cxl()
1301 dvsec_cxl_mld(d, where); in cap_dvsec_cxl()
1312 cap_dvsec(struct device *d, int where) in cap_dvsec() argument
1315 if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) in cap_dvsec()
1321 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); in cap_dvsec()
1326 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2); in cap_dvsec()
1330 cap_dvsec_cxl(d, id, rev, where, len); in cap_dvsec()
1336 cap_evendor(struct device *d, int where) in cap_evendor() argument
1341 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4)) in cap_evendor()
1347 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER); in cap_evendor()
1369 cap_l1pm(struct device *d, int where) in cap_l1pm() argument
1379 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) in cap_l1pm()
1385 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); in cap_l1pm()
1404 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); in cap_l1pm()
1426 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); in cap_l1pm()
1440 cap_ptm(struct device *d, int where) in cap_ptm() argument
1450 if (!config_fetch(d, where + 4, 8)) in cap_ptm()
1456 buff = get_conf_long(d, where + 4); in cap_ptm()
1477 buff = get_conf_long(d, where + 8); in cap_ptm()
1522 cap_rebar(struct device *d, int where, int virtual) in cap_rebar() argument
1538 where += 4; in cap_rebar()
1541 if (!config_fetch(d, where, 8)) in cap_rebar()
1547 sizes_buffer = get_conf_long(d, where) >> 4; in cap_rebar()
1548 where += 4; in cap_rebar()
1549 control_buffer = get_conf_long(d, where); in cap_rebar()
1588 cap_doe(struct device *d, int where) in cap_doe() argument
1597 if (!config_fetch(d, where + PCI_DOE_CAP, 0x14)) in cap_doe()
1603 l = get_conf_long(d, where + PCI_DOE_CAP); in cap_doe()
1610 l = get_conf_long(d, where + PCI_DOE_CTL); in cap_doe()
1614 l = get_conf_long(d, where + PCI_DOE_STS); in cap_doe()
1643 cap_ide(struct device *d, int where) in cap_ide() argument
1656 if (!config_fetch(d, where + PCI_IDE_CAP, 8)) in cap_ide()
1662 l = get_conf_long(d, where + PCI_IDE_CAP); in cap_ide()
1681 l = get_conf_long(d, where + PCI_IDE_CTL); in cap_ide()
1686 off = where + PCI_IDE_LINK_STREAM; in cap_ide()
1857 cap_dev3(struct device *d, int where) in cap_dev3() argument
1868 if (!config_fetch(d, where + PCI_DEV3_DEVCAP3, 4)) in cap_dev3()
1870 devcap3 = get_conf_long(d, where + PCI_DEV3_DEVCAP3); in cap_dev3()
1888 if (!config_fetch(d, where + PCI_DEV3_DEVCTL3, 2)) in cap_dev3()
1890 devctl3 = get_conf_word(d, where + PCI_DEV3_DEVCTL3); in cap_dev3()
1903 if (!config_fetch(d, where + PCI_DEV3_DEVSTA3, 2)) in cap_dev3()
1905 devsta3 = get_conf_word(d, where + PCI_DEV3_DEVSTA3); in cap_dev3()
1916 int where = 0x100; in show_ext_caps() local
1924 if (!config_fetch(d, where, 4)) in show_ext_caps()
1926 header = get_conf_long(d, where); in show_ext_caps()
1931 printf("\tCapabilities: [%03x", where); in show_ext_caps()
1935 if (been_there[where]++) in show_ext_caps()
1946 cap_aer(d, where, type); in show_ext_caps()
1949 cap_dpc(d, where); in show_ext_caps()
1953 cap_vc(d, where); in show_ext_caps()
1956 cap_dsn(d, where); in show_ext_caps()
1962 cap_rclink(d, where); in show_ext_caps()
1968 cap_rcec(d, where); in show_ext_caps()
1977 cap_evendor(d, where); in show_ext_caps()
1980 cap_acs(d, where); in show_ext_caps()
1983 cap_ari(d, where); in show_ext_caps()
1986 cap_ats(d, where); in show_ext_caps()
1989 cap_sriov(d, where); in show_ext_caps()
1995 cap_multicast(d, where, type); in show_ext_caps()
1998 cap_pri(d, where); in show_ext_caps()
2001 cap_rebar(d, where, 0); in show_ext_caps()
2007 cap_tph(d, where); in show_ext_caps()
2010 cap_ltr(d, where); in show_ext_caps()
2013 cap_sec(d, where); in show_ext_caps()
2019 cap_pasid(d, where); in show_ext_caps()
2025 cap_l1pm(d, where); in show_ext_caps()
2028 cap_ptm(d, where); in show_ext_caps()
2040 cap_dvsec(d, where); in show_ext_caps()
2043 cap_rebar(d, where, 1); in show_ext_caps()
2049 cap_phy_16gt(d, where); in show_ext_caps()
2052 cap_lmr(d, where); in show_ext_caps()
2061 cap_phy_32gt(d, where); in show_ext_caps()
2064 cap_doe(d, where); in show_ext_caps()
2067 cap_ide(d, where); in show_ext_caps()
2070 cap_phy_64gt(d, where); in show_ext_caps()
2073 cap_dev3(d, where); in show_ext_caps()
2079 where = (header >> 20) & ~3; in show_ext_caps()
2080 } while (where); in show_ext_caps()