Lines Matching refs:l
128 u32 l, l0, l1, l2, l3; in cap_aer() local
138 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); in cap_aer()
142 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), in cap_aer()
143 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), in cap_aer()
144 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), in cap_aer()
145 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL), in cap_aer()
146 FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP), in cap_aer()
147 FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED), in cap_aer()
148 FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED), in cap_aer()
149 FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK), in cap_aer()
150 FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED)); in cap_aer()
151 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK); in cap_aer()
155 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), in cap_aer()
156 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), in cap_aer()
157 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), in cap_aer()
158 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL), in cap_aer()
159 FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP), in cap_aer()
160 FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED), in cap_aer()
161 FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED), in cap_aer()
162 FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK), in cap_aer()
163 FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED)); in cap_aer()
164 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER); in cap_aer()
168 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), in cap_aer()
169 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), in cap_aer()
170 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), in cap_aer()
171 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL), in cap_aer()
172 FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP), in cap_aer()
173 FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED), in cap_aer()
174 FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED), in cap_aer()
175 FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK), in cap_aer()
176 FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED)); in cap_aer()
177 l = get_conf_long(d, where + PCI_ERR_COR_STATUS); in cap_aer()
180 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), in cap_aer()
181 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE), in cap_aer()
182 FLAG(l, PCI_ERR_COR_INTERNAL), FLAG(l, PCI_ERR_COR_HDRLOG_OVER)); in cap_aer()
183 l = get_conf_long(d, where + PCI_ERR_COR_MASK); in cap_aer()
186 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), in cap_aer()
187 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE), in cap_aer()
188 FLAG(l, PCI_ERR_COR_INTERNAL), FLAG(l, PCI_ERR_COR_HDRLOG_OVER)); in cap_aer()
189 l = get_conf_long(d, where + PCI_ERR_CAP); in cap_aer()
192 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), in cap_aer()
193 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE), in cap_aer()
194 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE), in cap_aer()
195 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG)); in cap_aer()
208 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); in cap_aer()
210 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN), in cap_aer()
211 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN), in cap_aer()
212 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN)); in cap_aer()
214 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); in cap_aer()
217 FLAG(l, PCI_ERR_ROOT_COR_RCV), in cap_aer()
218 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV), in cap_aer()
219 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV), in cap_aer()
220 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV), in cap_aer()
221 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL), in cap_aer()
222 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV), in cap_aer()
223 FLAG(l, PCI_ERR_ROOT_FATAL_RCV), in cap_aer()
224 PCI_ERR_MSG_NUM(l)); in cap_aer()
236 u16 l; in cap_dpc() local
245 l = get_conf_word(d, where + PCI_DPC_CAP); in cap_dpc()
247 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK), in cap_dpc()
248 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR)); in cap_dpc()
250 l = get_conf_word(d, where + PCI_DPC_CTL); in cap_dpc()
252 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT), in cap_dpc()
253 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER), in cap_dpc()
254 FLAG(l, PCI_DPC_CTL_DL_ACTIVE)); in cap_dpc()
256 l = get_conf_word(d, where + PCI_DPC_STATUS); in cap_dpc()
258 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT), in cap_dpc()
259 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l)); in cap_dpc()
261 l = get_conf_word(d, where + PCI_DPC_SOURCE); in cap_dpc()
262 printf("\t\tSource:\t%04x\n", l); in cap_dpc()
336 u32 l; in cap_pri() local
352 l = get_conf_long(d, where + PCI_PRI_MAX_REQ); in cap_pri()
353 printf("\t\tPage Request Capacity: %08x, ", l); in cap_pri()
354 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); in cap_pri()
355 printf("Page Request Allocation: %08x\n", l); in cap_pri()
385 u32 l; in cap_sriov() local
395 l = get_conf_long(d, where + PCI_IOV_CAP); in cap_sriov()
397 FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l)); in cap_sriov()
419 l = get_conf_long(d, where + PCI_IOV_SUPPS); in cap_sriov()
420 printf("\t\tSupported Page Size: %08x, ", l); in cap_sriov()
421 l = get_conf_long(d, where + PCI_IOV_SYSPS); in cap_sriov()
422 printf("System Page Size: %08x\n", l); in cap_sriov()
429 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i); in cap_sriov()
430 if (l == 0xffffffff) in cap_sriov()
431 l = 0; in cap_sriov()
432 if (!l) in cap_sriov()
435 addr = l & PCI_ADDR_MEM_MASK; in cap_sriov()
436 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK; in cap_sriov()
446 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-"); in cap_sriov()
449 l = get_conf_long(d, where + PCI_IOV_MSAO); in cap_sriov()
450 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l), in cap_sriov()
451 PCI_IOV_MSA_BIR(l)); in cap_sriov()
458 u32 l; in cap_multicast() local
480 l = get_conf_long(d, where + PCI_MCAST_BAR + 4); in cap_multicast()
481 bar |= (u64) l << 32; in cap_multicast()
485 l = get_conf_long(d, where + PCI_MCAST_RCV + 4); in cap_multicast()
486 rcv |= (u64) l << 32; in cap_multicast()
489 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4); in cap_multicast()
490 block |= (u64) l << 32; in cap_multicast()
493 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4); in cap_multicast()
494 block |= (u64) l << 32; in cap_multicast()
500 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4); in cap_multicast()
501 bar |= (u64) l << 32; in cap_multicast()
1022 u32 l; in dvsec_cxl_gpf_device() local
1057 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW); in dvsec_cxl_gpf_device()
1058 printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l); in dvsec_cxl_gpf_device()
1134 u32 l, data; in dvsec_cxl_flex_bus() local
1192 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA); in dvsec_cxl_flex_bus()
1193 data = BITS(l, 0, 24); in dvsec_cxl_flex_bus()
1202 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2); in dvsec_cxl_flex_bus()
1203 printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT)); in dvsec_cxl_flex_bus()
1205 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2); in dvsec_cxl_flex_bus()
1206 printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT)); in dvsec_cxl_flex_bus()
1208 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2); in dvsec_cxl_flex_bus()
1209 nop = BITS(l, 0, 2); in dvsec_cxl_flex_bus()
1590 u32 l; in cap_doe() local
1603 l = get_conf_long(d, where + PCI_DOE_CAP); in cap_doe()
1605 FLAG(l, PCI_DOE_CAP_INT_SUPP)); in cap_doe()
1606 if (l & PCI_DOE_CAP_INT_SUPP) in cap_doe()
1608 PCI_DOE_CAP_INT_MSG(l)); in cap_doe()
1610 l = get_conf_long(d, where + PCI_DOE_CTL); in cap_doe()
1612 FLAG(l, PCI_DOE_CTL_INT)); in cap_doe()
1614 l = get_conf_long(d, where + PCI_DOE_STS); in cap_doe()
1616 FLAG(l, PCI_DOE_STS_BUSY), in cap_doe()
1617 FLAG(l, PCI_DOE_STS_INT), in cap_doe()
1618 FLAG(l, PCI_DOE_STS_ERROR), in cap_doe()
1619 FLAG(l, PCI_DOE_STS_OBJECT_READY)); in cap_doe()
1631 static const char *ide_alg(char *buf, size_t len, u32 l) in ide_alg() argument
1635 if (l == 0) in ide_alg()
1636 snprintf(buf, len, "%s", algo[l]); in ide_alg()
1648 u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j; in cap_ide() local
1662 l = get_conf_long(d, where + PCI_IDE_CAP); in cap_ide()
1663 if (l & PCI_IDE_CAP_LINK_IDE_SUPP) in cap_ide()
1664 linknum = PCI_IDE_CAP_LINK_TC_NUM(l) + 1; in cap_ide()
1665 if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP) in cap_ide()
1666 selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1; in cap_ide()
1671 FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP), in cap_ide()
1672 FLAG(l, PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP), in cap_ide()
1673 FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP), in cap_ide()
1674 FLAG(l, PCI_IDE_CAP_PCRC_SUPP), in cap_ide()
1675 FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP), in cap_ide()
1676 ide_alg(buf2, sizeof(buf2), PCI_IDE_CAP_ALG(l)), in cap_ide()
1677 PCI_IDE_CAP_LINK_TC_NUM(l) + 1, in cap_ide()
1678 FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP) in cap_ide()
1681 l = get_conf_long(d, where + PCI_IDE_CTL); in cap_ide()
1683 FLAG(l, PCI_IDE_CTL_FLOWTHROUGH_IDE)); in cap_ide()
1699 l = get_conf_long(d, off); in cap_ide()
1703 FLAG(l, PCI_IDE_LINK_CTL_EN), in cap_ide()
1704 aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)], in cap_ide()
1705 aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)], in cap_ide()
1706 aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)], in cap_ide()
1707 FLAG(l, PCI_IDE_LINK_CTL_EN), in cap_ide()
1708 TABLE(hdr_enc_mode, PCI_IDE_LINK_CTL_PART_ENC(l), buf1), in cap_ide()
1709 ide_alg(buf2, sizeof(buf2), PCI_IDE_LINK_CTL_ALG(l)), in cap_ide()
1710 PCI_IDE_LINK_CTL_TC(l), in cap_ide()
1711 PCI_IDE_LINK_CTL_ID(l) in cap_ide()
1716 l = get_conf_long(d, off); in cap_ide()
1720 TABLE(stream_state, PCI_IDE_LINK_STS_STATUS(l), buf1), in cap_ide()
1721 FLAG(l, PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK)); in cap_ide()
1736 l = get_conf_long(d, off); in cap_ide()
1740 PCI_IDE_SEL_CAP_BLOCKS_NUM(l)); in cap_ide()
1742 addrnum = PCI_IDE_SEL_CAP_BLOCKS_NUM(l); in cap_ide()
1745 l = get_conf_long(d, off); in cap_ide()
1750 FLAG(l, PCI_IDE_SEL_CTL_EN), in cap_ide()
1751 aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)], in cap_ide()
1752 aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)], in cap_ide()
1753 aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)], in cap_ide()
1754 FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN), in cap_ide()
1755 FLAG(l, PCI_IDE_SEL_CTL_CFG_EN), in cap_ide()
1756 TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1), in cap_ide()
1757 ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)), in cap_ide()
1758 PCI_IDE_SEL_CTL_TC(l), in cap_ide()
1759 PCI_IDE_SEL_CTL_ID(l), in cap_ide()
1760 (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : "" in cap_ide()
1765 l = get_conf_long(d, off); in cap_ide()
1769 TABLE(stream_state, PCI_IDE_SEL_STS_STATUS(l), buf1), in cap_ide()
1770 FLAG(l, PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK)); in cap_ide()
1774 l = get_conf_long(d, off); in cap_ide()
1782 PCI_IDE_SEL_RID_1_LIMIT(l), in cap_ide()
1797 l = get_conf_long(d, off); in cap_ide()
1800 limit |= (PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l) << 20) | 0xFFFFF; in cap_ide()
1803 base |= PCI_IDE_SEL_ADDR_1_BASE_LOW(l) << 20; in cap_ide()
1808 FLAG(l, PCI_IDE_SEL_ADDR_1_VALID), in cap_ide()