Lines Matching refs:get_conf_long
27 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); in cap_tph()
118 t1 = get_conf_long(d, where + 4); in cap_dsn()
119 t2 = get_conf_long(d, where + 8); in cap_dsn()
138 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); in cap_aer()
151 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK); in cap_aer()
164 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER); in cap_aer()
177 l = get_conf_long(d, where + PCI_ERR_COR_STATUS); in cap_aer()
183 l = get_conf_long(d, where + PCI_ERR_COR_MASK); in cap_aer()
189 l = get_conf_long(d, where + PCI_ERR_CAP); in cap_aer()
197 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG); in cap_aer()
198 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4); in cap_aer()
199 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); in cap_aer()
200 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); in cap_aer()
208 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); in cap_aer()
214 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); in cap_aer()
352 l = get_conf_long(d, where + PCI_PRI_MAX_REQ); in cap_pri()
354 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); in cap_pri()
395 l = get_conf_long(d, where + PCI_IOV_CAP); in cap_sriov()
419 l = get_conf_long(d, where + PCI_IOV_SUPPS); in cap_sriov()
421 l = get_conf_long(d, where + PCI_IOV_SYSPS); in cap_sriov()
429 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i); in cap_sriov()
440 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4)); in cap_sriov()
449 l = get_conf_long(d, where + PCI_IOV_MSAO); in cap_sriov()
479 bar = get_conf_long(d, where + PCI_MCAST_BAR); in cap_multicast()
480 l = get_conf_long(d, where + PCI_MCAST_BAR + 4); in cap_multicast()
484 rcv = get_conf_long(d, where + PCI_MCAST_RCV); in cap_multicast()
485 l = get_conf_long(d, where + PCI_MCAST_RCV + 4); in cap_multicast()
488 block = get_conf_long(d, where + PCI_MCAST_BLOCK); in cap_multicast()
489 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4); in cap_multicast()
492 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS); in cap_multicast()
493 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4); in cap_multicast()
499 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR); in cap_multicast()
500 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4); in cap_multicast()
530 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1); in cap_vc()
531 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2); in cap_vc()
569 rcap = get_conf_long(d, pos); in cap_vc()
570 rctrl = get_conf_long(d, pos+4); in cap_vc()
615 esd = get_conf_long(d, where + PCI_RCLINK_ESD); in cap_rclink()
634 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC); in cap_rclink()
635 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR); in cap_rclink()
636 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4); in cap_rclink()
671 u32 hdr = get_conf_long(d, where); in cap_rcec()
673 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); in cap_rcec()
706 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); in cap_rcec()
749 u32 status = get_conf_long(d, where + PCI_16GT_STATUS); in cap_phy_16gt()
785 u32 cap = get_conf_long(d, where + PCI_32GT_CAP); in cap_phy_32gt()
786 u32 ctl = get_conf_long(d, where + PCI_32GT_CTL); in cap_phy_32gt()
787 u32 status = get_conf_long(d, where + PCI_32GT_STATUS); in cap_phy_32gt()
831 u32 status = get_conf_long(d, where + PCI_64GT_STATUS); in cap_phy_64gt()
926 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32; in dvsec_cxl_device()
927 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO); in dvsec_cxl_device()
928 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32; in dvsec_cxl_device()
929 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO); in dvsec_cxl_device()
932 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32; in dvsec_cxl_device()
933 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO); in dvsec_cxl_device()
934 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32; in dvsec_cxl_device()
935 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO); in dvsec_cxl_device()
997 u32 lo = get_conf_long(d, pos); in dvsec_cxl_register_locator()
998 u32 hi = get_conf_long(d, pos + 4); in dvsec_cxl_register_locator()
1057 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW); in dvsec_cxl_gpf_device()
1192 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA); in dvsec_cxl_flex_bus()
1202 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2); in dvsec_cxl_flex_bus()
1205 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2); in dvsec_cxl_flex_bus()
1208 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2); in dvsec_cxl_flex_bus()
1321 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); in cap_dvsec()
1326 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2); in cap_dvsec()
1347 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER); in cap_evendor()
1385 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); in cap_l1pm()
1404 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); in cap_l1pm()
1426 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); in cap_l1pm()
1456 buff = get_conf_long(d, where + 4); in cap_ptm()
1477 buff = get_conf_long(d, where + 8); in cap_ptm()
1547 sizes_buffer = get_conf_long(d, where) >> 4; in cap_rebar()
1549 control_buffer = get_conf_long(d, where); in cap_rebar()
1603 l = get_conf_long(d, where + PCI_DOE_CAP); in cap_doe()
1610 l = get_conf_long(d, where + PCI_DOE_CTL); in cap_doe()
1614 l = get_conf_long(d, where + PCI_DOE_STS); in cap_doe()
1662 l = get_conf_long(d, where + PCI_IDE_CAP); in cap_ide()
1681 l = get_conf_long(d, where + PCI_IDE_CTL); in cap_ide()
1699 l = get_conf_long(d, off); in cap_ide()
1716 l = get_conf_long(d, off); in cap_ide()
1736 l = get_conf_long(d, off); in cap_ide()
1745 l = get_conf_long(d, off); in cap_ide()
1765 l = get_conf_long(d, off); in cap_ide()
1774 l = get_conf_long(d, off); in cap_ide()
1775 l2 = get_conf_long(d, off + 4); in cap_ide()
1797 l = get_conf_long(d, off); in cap_ide()
1798 limit = get_conf_long(d, off + 4); in cap_ide()
1801 base = get_conf_long(d, off + 8); in cap_ide()
1870 devcap3 = get_conf_long(d, where + PCI_DEV3_DEVCAP3); in cap_dev3()
1926 header = get_conf_long(d, where); in show_ext_caps()