Lines Matching refs:x
898 #define PCI_EXP_DEVCAP2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ argument
907 #define PCI_EXP_DEVCAP2_TPH_COMP(x) (((x) >> 12) & 3) /* TPH Completer Supported */ argument
908 #define PCI_EXP_DEVCAP2_LN_CLS(x) (((x) >> 14) & 3) /* LN System CLS Supported */ argument
911 #define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported */ argument
914 #define PCI_EXP_DEVCAP2_MEE_TLP(x) (((x) >> 22) & 3) /* Max End-End TLP Prefixes */ argument
915 #define PCI_EXP_DEVCAP2_EPR(x) (((x) >> 24) & 3) /* Emergency Power Reduction Supported */ argument
919 #define PCI_EXP_DEVCTL2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ argument
929 #define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ argument
933 #define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f) argument
939 #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ argument
942 #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */ argument
943 #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ argument
946 #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance Preset/De-emphasis */ argument
948 #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */ argument
956 #define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */ argument
957 #define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */ argument
1039 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ argument
1061 #define PCI_ERR_MSG_NUM(x) (((x) >> 27) & 0x1f) /* MSI/MSI-X vector */ argument
1077 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ argument
1078 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ argument
1079 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ argument
1080 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ argument
1081 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ argument
1082 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ argument
1084 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ argument
1117 #define PCI_CXL_DEV_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */ argument
1123 #define PCI_CXL_DEV_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */ argument
1124 #define PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */ argument
1148 #define PCI_CXL_RANGE_TYPE(x) (((x) >> 2) & 0x7) argument
1149 #define PCI_CXL_RANGE_CLASS(x) (((x) >> 5) & 0x7) argument
1150 #define PCI_CXL_RANGE_INTERLEAVE(x) (((x) >> 8) & 0x1f) argument
1151 #define PCI_CXL_RANGE_TIMEOUT(x) (((x) >> 13) & 0x7) argument
1274 #define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */ argument
1289 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ argument
1293 #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ argument
1297 #define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */ argument
1299 #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ argument
1306 #define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */ argument
1328 #define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */ argument
1329 #define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */ argument
1333 #define PCI_MCAST_CAP_MAX_GROUP(x) ((x) & 0x3f) argument
1334 #define PCI_MCAST_CAP_WIN_SIZE(x) (((x) >> 8) & 0x3f) argument
1337 #define PCI_MCAST_CTRL_NUM_GROUP(x) ((x) & 0x3f) argument
1340 #define PCI_MCAST_BAR_INDEX_POS(x) ((u32) ((x) & 0x3f)) argument
1346 #define PCI_MCAST_OVL_SIZE(x) ((u32) ((x) & 0x3f)) argument
1383 #define PCI_SEC_LNKCTL3_ENBL_LOWER_SKP_OS_GEN_VEC(x) ((x >> 8) & 0x7F) argument
1410 #define PCI_32GT_CTL_MOD_TS_MODE(x) (((x) >> 8) & 0x7) /* Modified TS Usage Mode Selected */ argument
1418 #define PCI_32GT_STATUS_RCV_ENH_LINK(x) (((x) >> 6) & 0x3) /* Received Enhanced Link Behavior Cont… argument
1444 #define PCI_PASID_CAP_WIDTH(x) (((x) >> 8) & 0x1f) /* Max PASID Width */ argument
1451 #define PCI_DPC_CAP_INT_MSG(x) ((x) & 0x1f) /* DPC Interrupt Message Number */ argument
1455 #define PCI_DPC_CAP_RP_LOG(x) (((x) >> 8) & 0xf) /* DPC RP PIO Log Size */ argument
1458 #define PCI_DPC_CTL_TRIGGER(x) ((x) & 0x3) /* DPC Trigger Enable */ argument
1467 #define PCI_DPC_STS_REASON(x) (((x) >> 1) & 0x3) /* DPC Trigger Reason */ argument
1470 #define PCI_DPC_STS_TRIGGER_EXT(x) (((x) >> 5) & 0x3) /* Trigger Reason Extension */ argument
1471 #define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */ argument
1491 #define PCI_DOE_CAP_INT_MSG(x) (((x) >> 1) & 0x7ff) /* DOE Interrupt Message Number */ argument
1515 #define PCI_DEV3_DEVCAP3_PORT_L0P_EXIT(x) (((x) >> 4) & 0x7) /* Port L0p Exit Latency */ argument
1516 #define PCI_DEV3_DEVCAP3_RETIMER_L0P_EXIT(x) (((x) >> 7) & 0x7) /* Retimer L0p Exit Latency */ argument
1525 #define PCI_DEV3_DEVCTL3_TARGET_LINK_WIDTH(x) (((x) >> 4) & 0x7) /* Target Link Width */ argument
1530 #define PCI_DEV3_DEVSTA3_INIT_LINK_WIDTH(x) ((x) & 0x7) /* Initial Link Width */ argument
1543 #define PCI_IDE_CAP_ALG(x) (((x) >> 8) & 0x1f) /* Supported Algorithms */ argument
1545 #define PCI_IDE_CAP_LINK_TC_NUM(x) (((x) >> 13) & 0x7) /* Number of TCs Supported for Link IDE */ argument
1546 #define PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(x) (((x) >> 16) & 0xff) /* Number of Selective IDE Strea… argument
1554 #define PCI_IDE_LINK_CTL_TX_AGGR_NPR(x)(((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */ argument
1555 #define PCI_IDE_LINK_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ argument
1556 #define PCI_IDE_LINK_CTL_TX_AGGR_CPL(x)(((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ argument
1558 #define PCI_IDE_LINK_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ argument
1559 #define PCI_IDE_LINK_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ argument
1560 #define PCI_IDE_LINK_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ argument
1561 #define PCI_IDE_LINK_CTL_ID(x) (((x) >> 24) & 0xff) /* Stream ID */ argument
1563 #define PCI_IDE_LINK_STS_STATUS(x) ((x) & 0xf) /* Link IDE Stream State */ argument
1567 #define PCI_IDE_SEL_CAP_BLOCKS_NUM(x) ((x) & 0xf) /* Number of Address Association Register Blocks… argument
1570 #define PCI_IDE_SEL_CTL_TX_AGGR_NPR(x) (((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */ argument
1571 #define PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ argument
1572 #define PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ argument
1575 #define PCI_IDE_SEL_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ argument
1576 #define PCI_IDE_SEL_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ argument
1577 #define PCI_IDE_SEL_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ argument
1579 #define PCI_IDE_SEL_CTL_ID(x) (((x) >> 24) & 0xff) /* Stream ID */ argument
1581 #define PCI_IDE_SEL_STS_STATUS(x) ((x) & 0xf) /* Selective IDE Stream State */ argument
1584 #define PCI_IDE_SEL_RID_1_LIMIT(x) (((x) >> 8) & 0xffff) /* RID Limit */ argument
1587 #define PCI_IDE_SEL_RID_2_BASE(x) (((x) >> 8) & 0xffff) /* RID Base */ argument
1588 #define PCI_IDE_SEL_RID_2_SEG_BASE(x) (((x) >> 24) & 0xff) /* Segmeng Base */ argument
1591 #define PCI_IDE_SEL_ADDR_1_BASE_LOW(x) (((x) >> 8) & 0xfff) /* Memory Base Lower */ argument
1592 #define PCI_IDE_SEL_ADDR_1_LIMIT_LOW(x)(((x) >> 20) & 0xfff) /* Memory Limit Lower */ argument