header.h: Fix type 1 header comment

Should be 0x35-0x37 is reserved.

Signed-off-by: Rong Tao <[email protected]>

Flit Mode and Device 3 Capability

header.h: Classes and capabilities from PCI Code and ID Assignment rev 1.18

libpci: add some missing PCI_CLASS constants

The names and values are taken from the pci.ids file.

lspci: Decode Physical Layer 64 GT/s extended capability register

lspci: Decode Physical Layer 16 GT/s and 32 GT/s extended capability registers

ls-ecaps: extend decode support for more fields for AER CE and UE status

Extend decode support for more fields for AER CE and UE status prior to
PCIe r6.0.

Signed-off-by: Shuai Xue <xueshuai@linux.

ls-ecaps: extend decode support for more fields for AER CE and UE status

Extend decode support for more fields for AER CE and UE status prior to
PCIe r6.0.

Signed-off-by: Shuai Xue <[email protected]>

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ls-ecaps: Correct the link state reporting

PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:

0000b Insecure
0010b Secure

The same definition applies to selecti

ls-ecaps: Correct the link state reporting

PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:

0000b Insecure
0010b Secure

The same definition applies to selective streams as well.
The existing code wrongly assumes "secure" is 0001b, fix that for both
link and selective streams.

While at this, add missing "Selective IDE for Configuration Requests Enable".
Also fix the base and limit parsing for the memory and RID ranges.

Fixes: 42fc4263ec0e ("ls-ecaps: Add decode support for IDE Extended Capability")
Signed-off-by: Alexey Kardashevskiy <[email protected]>

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lspci: Add TEE-IO extended capability bit

PCIe r6.1, sec 7.5.3.3 defines "TEE-IO Supported" in the PCI Express Device
Capabilities Register which indicates that the function implements
the TEE-IO fu

lspci: Add TEE-IO extended capability bit

PCIe r6.1, sec 7.5.3.3 defines "TEE-IO Supported" in the PCI Express Device
Capabilities Register which indicates that the function implements
the TEE-IO functionality as described by the TEE Device Interface Security
Protocol (TDISP, PCIe r6.1, chapter 11).

tests/cap-ide is an example of such device.

Signed-off-by: Alexey Kardashevskiy <[email protected]>

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ls-ecaps: Add decode support for IDE Extended Capability

IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 pri

ls-ecaps: Add decode support for IDE Extended Capability

IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 prints
offsets of the fields to make running setpci easier.

The example output is:

Capabilities: [830 v1] Integrity & Data Encryption
IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
IDECtl: FTEn-
SelectiveIDE#0 Cap: RID#=1
SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0
SelectiveIDE#0 Sta: insecure RecvChkFail-
SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0
SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0

[1] PCIe r6.0.1, sections 6.33, 7.9.26

Signed-off-by: Alexey Kardashevskiy <[email protected]>

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libpci: Add constants for Lane Margining at the Receiver Extended Capability

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

Constants for CXL capability should not change

When CXL capability decoding was upgraded to revision 2 by commit
c0ccce1b4cd5b42b17f2e8f7bae4031c311677ff, the value of PCI_CXL_DEV_LEN
in lib/header.

Constants for CXL capability should not change

When CXL capability decoding was upgraded to revision 2 by commit
c0ccce1b4cd5b42b17f2e8f7bae4031c311677ff, the value of PCI_CXL_DEV_LEN
in lib/header.h has changed.

This is probably not a good idea - programs using libpci can depend
on the exact value of this constant.

Let us revert PCI_CXL_DEV_LEN to the original value for revision 1
and add PCI_CXL_DEV_LEN_REV2 for the next revision.

Also, fixed a bug in the decoder which caused it to read past the
end of the buffer for a capability which is declared as revision 2,
but too short.

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Subject: lspci: Display PASID required attribute in Page Status Register.

Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Gro

Subject: lspci: Display PASID required attribute in Page Status Register.

Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Group Response (PRG)
messages when the corresponding page request had a PASID.

Signed-off-by: Ashok Raj <[email protected]>

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lspci: Decode PCIe DevCtl2 End-to-End TLP Prefix Blocking

Decode the PCIe DevCtl2 End-to-End TLP Prefix Blocking bit. The
"EETLPPrefixBlk" format is analogous to the existing "EETLPPrefix" format
u

lspci: Decode PCIe DevCtl2 End-to-End TLP Prefix Blocking

Decode the PCIe DevCtl2 End-to-End TLP Prefix Blocking bit. The
"EETLPPrefixBlk" format is analogous to the existing "EETLPPrefix" format
used for the corresponding DevCap2 bit.

Signed-off-by: Bjorn Helgaas <[email protected]>

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lspci: Decode PCIe DevCtl2 Emergency Power Reduction Request

Decode the PCIe DevCtl2 Emergency Power Reduction Request bit.

Signed-off-by: Bjorn Helgaas <[email protected]>

lspci: Decode PCIe DevCtl2 ID-Based Ordering Enables

Decode the PCIe DevCtl2 ID-Based Ordering Enable bits.

Signed-off-by: Bjorn Helgaas <[email protected]>

Add support for 32.0 GT/s header

lib: fixup DOE status register bit

The error bit is specified by the 2nd (zero indexed) bit
in the status register, so the respective bit value is 4 (PCI Base Spec
6.0.1). Let's fix that up.

Signed

lib: fixup DOE status register bit

The error bit is specified by the 2nd (zero indexed) bit
in the status register, so the respective bit value is 4 (PCI Base Spec
6.0.1). Let's fix that up.

Signed-off-by: Wilfred Mallawa <[email protected]>

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Update license comments and added SPDX license identifiers

Previously, the only information about the specific version of GPL
was present in the README and individual source files mentioned only
GPL

Update license comments and added SPDX license identifiers

Previously, the only information about the specific version of GPL
was present in the README and individual source files mentioned only
GPL alone.

Let us update all copyright comments to explicitly say "GPL v2+"
and also include the machine readable SPDX license identifier.

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CXL3.0: Add DVSEC CXLCtrl3 and missing CXLCtl2

8.1.3 PCIe DVSEC for CXL Devices

CXL: Fix Flex Bus DVSEC cap

lspci: Add support for Non-CXL Function Map DVSEC

Add Non-CXL Function Map DVSEC Registers 0-7 decoding according to
DVSEC Revision ID 0.

Signed-off-by: Jaxon Haws <[email protected]>

lspci: Add support for CXL MLD DVSEC

Add MLD DVSEC decoding for CXL device accoring to DVSEC revision ID 0.
Decode Number of Logical Devices Supported.

Signed-off-by: Jaxon Haws <[email protected]>

lspci: Add support for CXL GPF Port DVSEC

Add Global Persistent Flush DVSEC decoding for CXL port according to
DVSEC Revision ID 0.
Decode GPF Phase 1 Control and GPF Phase 2 Control.

Signed-off-by

lspci: Add support for CXL GPF Port DVSEC

Add Global Persistent Flush DVSEC decoding for CXL port according to
DVSEC Revision ID 0.
Decode GPF Phase 1 Control and GPF Phase 2 Control.

Signed-off-by: Jaxon Haws <[email protected]>

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lspci: Add support for CXL Flex Bus DVSEC

Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1,
capability decoding, control decoding, and status decoding.

Signed-off-by: Jaxon

lspci: Add support for CXL Flex Bus DVSEC

Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1,
capability decoding, control decoding, and status decoding.

Signed-off-by: Jaxon Haws <[email protected]>

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