Lines Matching refs:vectors

157 [SplatOpLowering for n-D vectors](https://github.com/tensorflow/mlir/commit/0a0c4867c6a6fcb0a2f17ef…
261 `vector<4x8x16x32xf32>`). This section discusses operations on vectors in LLVM
265 `llvm.insertvalue`). Such ops operate exclusively on 1-D vectors and aggregates
297 This distinction is also reflected in some of the operations. For `1-D` vectors,
300 vectors with `n>1`, and thus aggregate types at LLVM level, the more restrictive
312 vectors in memory. For `n-D`, vectors values that live in registers we can use
341 3.  Special intrinsics and native instructions in LLVM operate on `1-D` vectors.
360     day, HW vector sizes are generally fixed and multiple vectors will be needed
373 evolving to higher-dimensional physical vectors.
378 register file. The number of such vectors is fixed. Depending on the rank and
395 vectors when lowered to LLVM. This introduces the consequences on static vs
397 `shufflevector` on `n-D` vectors in MLIR only support static indices. Dynamic
410 3.  HW may support >1-D vectors with intrinsics for indirect addressing within
411     these vectors. These can be targeted thanks to explicit `vector_cast`
413     vectors + intrinsics.
433 To target accelerators that support higher dimensional vectors natively, we can
434 start from either `1-D` or `n-D` vectors in MLIR and use `vector.cast` to
458 #### Implication on calling external functions that operate on vectors
469 generic n-D vector types from MLIR to aggregates of 1-D LLVM vectors. In the
474 could become the unifying abstraction that people should target for 1-D vectors
484 target operations on coarser-grained vectors than the HW size and on which
485 unroll-and-jam is applied and patterns across multiple HW vectors can be