Lines Matching refs:lowering
21 lowering paths.
66 2. `Virtual Vector -> Hardware Vector` lowering is specified as a set of MLIR
67 lowering patterns that are specified manually for now.
68 3. `Hardware Vector -> LLVM` lowering is a mechanical process that is written
81 lowering choices and tradeoffs.
91 cost-based lowering decisions in MLIR even for `LLVM`. Specialized `CPU`
145 2. The lowering of `vector_transfer` ops legalizes `vector` load/store ops to
159 [VectorOuterProductOp lowering](https://github.com/tensorflow/mlir/commit/957b1ca9680b4aacabb3a480f…
223 lowering. The argument can be made that automatic vectorization on a loops + ops
252 This section describes the tradeoffs involved in lowering the MLIR n-D vector
319 flattened lowering of an MLIR n-D vector to an LLVM 1-D vector.
415 Alternatively, we argue that directly lowering to a linearized abstraction hides
436 appropriate constant. Then, the existing lowering to LLVM-IR immediately
440 the figure above) to lower the `vector.cast`. Accelerator -> LLVM lowering would
468 higher level of abstraction and allows the lowering of generic operations on
489 lowering from MLIR because: