Lines Matching refs:InstRWs
939 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
1073 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; in createInstRWClass()
1103 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef); in createInstRWClass()
1123 for (Record *OldRWDef : SchedClasses[OldSCIdx].InstRWs) { in createInstRWClass()
1136 SC.InstRWs.push_back(OldRWDef); in createInstRWClass()
1142 SC.InstRWs.push_back(InstRWDef); in createInstRWClass()
1237 if (!SchedClasses[Idx].InstRWs.empty()) in inferSchedClasses()
1273 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { in inferFromInstRWs()
1274 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); in inferFromInstRWs()
1275 Record *Rec = SchedClasses[SCIdx].InstRWs[I]; in inferFromInstRWs()
1897 for (Record *RW : SC.InstRWs) { in collectProcResources()
2012 const RecVec &InstRWs = SC.InstRWs; in checkCompleteness() local
2013 auto I = find_if(InstRWs, [&ProcModel](const Record *R) { in checkCompleteness()
2016 if (I == InstRWs.end()) { in checkCompleteness()