Lines Matching refs:LSD

157 ; CHECK-NEXT:    [[LSD:%.*]] = load i32, i32* [[ISD]], align 4
161 ; CHECK-NEXT:    [[PSD:%.*]] = add nsw i32 [[LSD]], 23
165 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100
168 ; CHECK-NEXT:    [[RSD:%.*]] = sdiv i32 [[PSD]], [[LSD]]
317 ; UNROLL-NO-VF-NEXT:    [[LSD:%.*]] = load i32, i32* [[ISD]], align 4
321 ; UNROLL-NO-VF-NEXT:    [[PSD:%.*]] = add nsw i32 [[LSD]], 23
325 ; UNROLL-NO-VF-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100
328 ; UNROLL-NO-VF-NEXT:    [[RSD:%.*]] = sdiv i32 [[PSD]], [[LSD]]
462 ; CHECK-NEXT:    [[LSD:%.*]] = load i32, i32* [[ISD]], align 4
465 ; CHECK-NEXT:    [[PSD:%.*]] = add nsw i32 [[LSD]], 23
466 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100
469 ; CHECK-NEXT:    [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]
547 ; UNROLL-NO-VF-NEXT:    [[LSD:%.*]] = load i32, i32* [[ISD]], align 4
550 ; UNROLL-NO-VF-NEXT:    [[PSD:%.*]] = add nsw i32 [[LSD]], 23
551 ; UNROLL-NO-VF-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100
554 ; UNROLL-NO-VF-NEXT:    [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]
670 ; CHECK-NEXT:    [[LSD:%.*]] = load i32, i32* [[ISD]], align 4
673 ; CHECK-NEXT:    [[PSD:%.*]] = add nsw i32 [[LSD]], 23
674 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100
675 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp sge i32 [[LSD]], 200
679 ; CHECK-NEXT:    [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]
767 ; UNROLL-NO-VF-NEXT:    [[LSD:%.*]] = load i32, i32* [[ISD]], align 4
770 ; UNROLL-NO-VF-NEXT:    [[PSD:%.*]] = add nsw i32 [[LSD]], 23
771 ; UNROLL-NO-VF-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[LSD]], 100
774 ; UNROLL-NO-VF-NEXT:    [[CMP2:%.*]] = icmp sge i32 [[LSD]], 200
777 ; UNROLL-NO-VF-NEXT:    [[SD1:%.*]] = sdiv i32 [[PSD]], [[LSD]]