Lines Matching refs:SIMD128

1 …als -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
3 …eep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
5 …-wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
7 …le-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
13 ; Test that basic SIMD128 arithmetic operations assemble as expected.
21 ; NO-SIMD128-NOT: i8x16
22 ; SIMD128-NEXT: .functype add_v16i8 (v128, v128) -> (v128){{$}}
23 ; SIMD128-NEXT: i8x16.add $push[[R:[0-9]+]]=, $0, $1{{$}}
24 ; SIMD128-NEXT: return $pop[[R]]{{$}}
31 ; NO-SIMD128-NOT: i8x16
32 ; SIMD128-NEXT: .functype sub_v16i8 (v128, v128) -> (v128){{$}}
33 ; SIMD128-NEXT: i8x16.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
34 ; SIMD128-NEXT: return $pop[[R]]{{$}}
42 ; NO-SIMD128-NOT: i8x16
43 ; SIMD128-NOT: i8x16.mul
44 ; SIMD128: i8x16.extract_lane_u
45 ; SIMD128: i32.mul
52 ; NO-SIMD128-NOT: i8x16
53 ; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}}
54 ; SIMD128-NEXT: i8x16.min_s $push[[R:[0-9]+]]=, $0, $1{{$}}
55 ; SIMD128-NEXT: return $pop[[R]]{{$}}
63 ; NO-SIMD128-NOT: i8x16
64 ; SIMD128-NEXT: .functype min_u_v16i8 (v128, v128) -> (v128){{$}}
65 ; SIMD128-NEXT: i8x16.min_u $push[[R:[0-9]+]]=, $0, $1{{$}}
66 ; SIMD128-NEXT: return $pop[[R]]{{$}}
74 ; NO-SIMD128-NOT: i8x16
75 ; SIMD128-NEXT: .functype max_s_v16i8 (v128, v128) -> (v128){{$}}
76 ; SIMD128-NEXT: i8x16.max_s $push[[R:[0-9]+]]=, $0, $1{{$}}
77 ; SIMD128-NEXT: return $pop[[R]]{{$}}
85 ; NO-SIMD128-NOT: i8x16
86 ; SIMD128-NEXT: .functype max_u_v16i8 (v128, v128) -> (v128){{$}}
87 ; SIMD128-NEXT: i8x16.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
88 ; SIMD128-NEXT: return $pop[[R]]{{$}}
96 ; NO-SIMD128-NOT: i8x16
97 ; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}
98 ; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
99 ; SIMD128-NEXT: return $pop[[R]]{{$}}
110 ; NO-SIMD128-NOT: i8x16
111 ; SIMD128-NEXT: .functype avgr_u_v16i8_wrap (v128, v128) -> (v128){{$}}
112 ; SIMD128-NOT: i8x16.avgr_u
123 ; NO-SIMD128-NOT: i8x16
124 ; SIMD128-NEXT: .functype abs_v16i8 (v128) -> (v128){{$}}
125 ; SIMD128-NEXT: i8x16.abs $push[[R:[0-9]+]]=, $0{{$}}
126 ; SIMD128-NEXT: return $pop[[R]]{{$}}
135 ; NO-SIMD128-NOT: i8x16
136 ; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}}
137 ; SIMD128-NEXT: i8x16.neg $push[[R:[0-9]+]]=, $0{{$}}
138 ; SIMD128-NEXT: return $pop[[R]]{{$}}
147 ; NO-SIMD128-NOT: i8x16
148 ; SIMD128-NEXT: .functype shl_v16i8 (v128, i32) -> (v128){{$}}
149 ; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
150 ; SIMD128-NEXT: return $pop[[R]]{{$}}
161 ; NO-SIMD128-NOT: i8x16
162 ; SIMD128-NEXT: .functype shl_const_v16i8 (v128) -> (v128){{$}}
163 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5
164 ; SIMD128-NEXT: i8x16.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
165 ; SIMD128-NEXT: return $pop[[R]]{{$}}
174 ; NO-SIMD128-NOT: i8x16
175 ; SIMD128-NEXT: .functype shl_vec_v16i8 (v128, v128) -> (v128){{$}}
176 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
177 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
178 ; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}}
179 ; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}}
180 ; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]
181 ; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]]
183 ; SIMD128:      i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}}
184 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}}
185 ; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}}
186 ; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}}
187 ; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}}
188 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}}
189 ; SIMD128-NEXT: return $pop[[R]]{{$}}
196 ; NO-SIMD128-NOT: i8x16
197 ; SIMD128-NEXT: .functype shr_s_v16i8 (v128, i32) -> (v128){{$}}
198 ; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
199 ; SIMD128-NEXT: return $pop[[R]]{{$}}
210 ; NO-SIMD128-NOT: i8x16
211 ; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}}
212 ; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
213 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
214 ; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}}
215 ; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}}
216 ; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]
217 ; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]]
219 ; SIMD128:      i8x16.extract_lane_s $push[[L4:[0-9]+]]=, $0, 15{{$}}
220 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}}
221 ; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}}
222 ; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}}
223 ; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}}
224 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}}
225 ; SIMD128-NEXT: return $pop[[R]]{{$}}
232 ; NO-SIMD128-NOT: i8x16
233 ; SIMD128-NEXT: .functype shr_u_v16i8 (v128, i32) -> (v128){{$}}
234 ; SIMD128-NEXT: i8x16.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
235 ; SIMD128-NEXT: return $pop[[R]]{{$}}
246 ; NO-SIMD128-NOT: i8x16
247 ; SIMD128-NEXT: .functype shr_u_vec_v16i8 (v128, v128) -> (v128){{$}}
248 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
249 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
250 ; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}}
251 ; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}}
252 ; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]
253 ; SIMD128-NEXT: i8x16.splat $push[[M3:[0-9]+]]=, $pop[[M2]]
255 ; SIMD128:      i8x16.extract_lane_u $push[[L4:[0-9]+]]=, $0, 15{{$}}
256 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 15{{$}}
257 ; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 7{{$}}
258 ; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}}
259 ; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}}
260 ; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 15, $pop[[M6]]{{$}}
261 ; SIMD128-NEXT: return $pop[[R]]{{$}}
268 ; NO-SIMD128-NOT: v128
269 ; SIMD128-NEXT: .functype and_v16i8 (v128, v128) -> (v128){{$}}
270 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
271 ; SIMD128-NEXT: return $pop[[R]]{{$}}
278 ; NO-SIMD128-NOT: v128
279 ; SIMD128-NEXT: .functype or_v16i8 (v128, v128) -> (v128){{$}}
280 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
281 ; SIMD128-NEXT: return $pop[[R]]{{$}}
288 ; NO-SIMD128-NOT: v128
289 ; SIMD128-NEXT: .functype xor_v16i8 (v128, v128) -> (v128){{$}}
290 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
291 ; SIMD128-NEXT: return $pop[[R]]{{$}}
298 ; NO-SIMD128-NOT: v128
299 ; SIMD128-NEXT: .functype not_v16i8 (v128) -> (v128){{$}}
300 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
301 ; SIMD128-NEXT: return $pop[[R]]{{$}}
311 ; NO-SIMD128-NOT: v128
312 ; SIMD128-NEXT: .functype andnot_v16i8 (v128, v128) -> (v128){{$}}
313 ; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
314 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
315 ; SIMD128-FAST-NEXT: v128.not
316 ; SIMD128-FAST-NEXT: v128.and
317 ; SIMD128-FAST-NEXT: return
327 ; NO-SIMD128-NOT: v128
328 ; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
329 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
330 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
331 ; SIMD128-FAST-NEXT: v128.and
332 ; SIMD128-FAST-NEXT: v128.not
333 ; SIMD128-FAST-NEXT: v128.and
334 ; SIMD128-FAST-NEXT: v128.or
335 ; SIMD128-FAST-NEXT: return
350 ; NO-SIMD128-NOT: i16x8
351 ; SIMD128-NEXT: .functype add_v8i16 (v128, v128) -> (v128){{$}}
352 ; SIMD128-NEXT: i16x8.add $push[[R:[0-9]+]]=, $0, $1{{$}}
353 ; SIMD128-NEXT: return $pop[[R]]{{$}}
360 ; NO-SIMD128-NOT: i16x8
361 ; SIMD128-NEXT: .functype sub_v8i16 (v128, v128) -> (v128){{$}}
362 ; SIMD128-NEXT: i16x8.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
363 ; SIMD128-NEXT: return $pop[[R]]{{$}}
370 ; NO-SIMD128-NOT: i16x8
371 ; SIMD128-NEXT: .functype mul_v8i16 (v128, v128) -> (v128){{$}}
372 ; SIMD128-NEXT: i16x8.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
373 ; SIMD128-NEXT: return $pop[[R]]{{$}}
380 ; NO-SIMD128-NOT: i16x8
381 ; SIMD128-NEXT: .functype min_s_v8i16 (v128, v128) -> (v128){{$}}
382 ; SIMD128-NEXT: i16x8.min_s $push[[R:[0-9]+]]=, $0, $1{{$}}
383 ; SIMD128-NEXT: return $pop[[R]]{{$}}
391 ; NO-SIMD128-NOT: i16x8
392 ; SIMD128-NEXT: .functype min_u_v8i16 (v128, v128) -> (v128){{$}}
393 ; SIMD128-NEXT: i16x8.min_u $push[[R:[0-9]+]]=, $0, $1{{$}}
394 ; SIMD128-NEXT: return $pop[[R]]{{$}}
402 ; NO-SIMD128-NOT: i16x8
403 ; SIMD128-NEXT: .functype max_s_v8i16 (v128, v128) -> (v128){{$}}
404 ; SIMD128-NEXT: i16x8.max_s $push[[R:[0-9]+]]=, $0, $1{{$}}
405 ; SIMD128-NEXT: return $pop[[R]]{{$}}
413 ; NO-SIMD128-NOT: i16x8
414 ; SIMD128-NEXT: .functype max_u_v8i16 (v128, v128) -> (v128){{$}}
415 ; SIMD128-NEXT: i16x8.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
416 ; SIMD128-NEXT: return $pop[[R]]{{$}}
424 ; NO-SIMD128-NOT: i16x8
425 ; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}
426 ; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
427 ; SIMD128-NEXT: return $pop[[R]]{{$}}
436 ; NO-SIMD128-NOT: i16x8
437 ; SIMD128-NEXT: .functype avgr_u_v8i16_wrap (v128, v128) -> (v128){{$}}
438 ; SIMD128-NOT: i16x8.avgr_u
447 ; NO-SIMD128-NOT: i16x8
448 ; SIMD128-NEXT: .functype abs_v8i16 (v128) -> (v128){{$}}
449 ; SIMD128-NEXT: i16x8.abs $push[[R:[0-9]+]]=, $0{{$}}
450 ; SIMD128-NEXT: return $pop[[R]]{{$}}
459 ; NO-SIMD128-NOT: i16x8
460 ; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}}
461 ; SIMD128-NEXT: i16x8.neg $push[[R:[0-9]+]]=, $0{{$}}
462 ; SIMD128-NEXT: return $pop[[R]]{{$}}
470 ; NO-SIMD128-NOT: i16x8
471 ; SIMD128-NEXT: .functype shl_v8i16 (v128, i32) -> (v128){{$}}
472 ; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
473 ; SIMD128-NEXT: return $pop[[R]]{{$}}
483 ; NO-SIMD128-NOT: i16x8
484 ; SIMD128-NEXT: .functype shl_const_v8i16 (v128) -> (v128){{$}}
485 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5
486 ; SIMD128-NEXT: i16x8.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
487 ; SIMD128-NEXT: return $pop[[R]]{{$}}
495 ; NO-SIMD128-NOT: i16x8
496 ; SIMD128-NEXT: .functype shl_vec_v8i16 (v128, v128) -> (v128){{$}}
497 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
498 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
499 ; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}}
500 ; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}}
501 ; SIMD128-NEXT: i32.shl $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}}
502 ; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}}
504 ; SIMD128:      i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}}
505 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}}
506 ; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}}
507 ; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}}
508 ; SIMD128-NEXT: i32.shl $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}}
509 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}}
510 ; SIMD128-NEXT: return $pop[[R]]{{$}}
517 ; NO-SIMD128-NOT: i16x8
518 ; SIMD128-NEXT: .functype shr_s_v8i16 (v128, i32) -> (v128){{$}}
519 ; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
520 ; SIMD128-NEXT: return $pop[[R]]{{$}}
530 ; NO-SIMD128-NOT: i16x8
531 ; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}}
532 ; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
533 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
534 ; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}}
535 ; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}}
536 ; SIMD128-NEXT: i32.shr_s $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}}
537 ; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}}
539 ; SIMD128:      i16x8.extract_lane_s $push[[L4:[0-9]+]]=, $0, 7{{$}}
540 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}}
541 ; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}}
542 ; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}}
543 ; SIMD128-NEXT: i32.shr_s $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}}
544 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}}
545 ; SIMD128-NEXT: return $pop[[R]]{{$}}
552 ; NO-SIMD128-NOT: i16x8
553 ; SIMD128-NEXT: .functype shr_u_v8i16 (v128, i32) -> (v128){{$}}
554 ; SIMD128-NEXT: i16x8.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
555 ; SIMD128-NEXT: return $pop[[R]]{{$}}
565 ; NO-SIMD128-NOT: i16x8
566 ; SIMD128-NEXT: .functype shr_u_vec_v8i16 (v128, v128) -> (v128){{$}}
567 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
568 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
569 ; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}}
570 ; SIMD128-NEXT: i32.and $push[[M1:[0-9]+]]=, $pop[[L1]], $pop[[M0]]{{$}}
571 ; SIMD128-NEXT: i32.shr_u $push[[M2:[0-9]+]]=, $pop[[L0]], $pop[[M1]]{{$}}
572 ; SIMD128-NEXT: i16x8.splat $push[[M3:[0-9]+]]=, $pop[[M2]]{{$}}
574 ; SIMD128:      i16x8.extract_lane_u $push[[L4:[0-9]+]]=, $0, 7{{$}}
575 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 7{{$}}
576 ; SIMD128-NEXT: i32.const $push[[M4:[0-9]+]]=, 15{{$}}
577 ; SIMD128-NEXT: i32.and $push[[M5:[0-9]+]]=, $pop[[L5]], $pop[[M4]]{{$}}
578 ; SIMD128-NEXT: i32.shr_u $push[[M6:[0-9]+]]=, $pop[[L4]], $pop[[M5]]{{$}}
579 ; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[M7:[0-9]+]], 7, $pop[[M6]]{{$}}
580 ; SIMD128-NEXT: return $pop[[R]]{{$}}
587 ; NO-SIMD128-NOT: v128
588 ; SIMD128-NEXT: .functype and_v8i16 (v128, v128) -> (v128){{$}}
589 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
590 ; SIMD128-NEXT: return $pop[[R]]{{$}}
597 ; NO-SIMD128-NOT: v128
598 ; SIMD128-NEXT: .functype or_v8i16 (v128, v128) -> (v128){{$}}
599 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
600 ; SIMD128-NEXT: return $pop[[R]]{{$}}
607 ; NO-SIMD128-NOT: v128
608 ; SIMD128-NEXT: .functype xor_v8i16 (v128, v128) -> (v128){{$}}
609 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
610 ; SIMD128-NEXT: return $pop[[R]]{{$}}
617 ; NO-SIMD128-NOT: v128
618 ; SIMD128-NEXT: .functype not_v8i16 (v128) -> (v128){{$}}
619 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
620 ; SIMD128-NEXT: return $pop[[R]]{{$}}
628 ; NO-SIMD128-NOT: v128
629 ; SIMD128-NEXT: .functype andnot_v8i16 (v128, v128) -> (v128){{$}}
630 ; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
631 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
632 ; SIMD128-FAST-NEXT: v128.not
633 ; SIMD128-FAST-NEXT: v128.and
634 ; SIMD128-FAST-NEXT: return
643 ; NO-SIMD128-NOT: v128
644 ; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
645 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
646 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
647 ; SIMD128-FAST-NEXT: v128.and
648 ; SIMD128-FAST-NEXT: v128.not
649 ; SIMD128-FAST-NEXT: v128.and
650 ; SIMD128-FAST-NEXT: v128.or
651 ; SIMD128-FAST-NEXT: return
663 ; NO-SIMD128-NOT: i16x8
664 ; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
665 ; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
666 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
679 ; NO-SIMD128-NOT: i16x8
680 ; SIMD128-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
681 ; SIMD128-SLOW-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
682 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
695 ; NO-SIMD128-NOT: i16x8
696 ; SIMD128-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
697 ; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
698 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
711 ; NO-SIMD128-NOT: i16x8
712 ; SIMD128-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
713 ; SIMD128-SLOW-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
714 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
730 ; NO-SIMD128-NOT: i32x4
731 ; SIMD128-NEXT: .functype add_v4i32 (v128, v128) -> (v128){{$}}
732 ; SIMD128-NEXT: i32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}}
733 ; SIMD128-NEXT: return $pop[[R]]{{$}}
740 ; NO-SIMD128-NOT: i32x4
741 ; SIMD128-NEXT: .functype sub_v4i32 (v128, v128) -> (v128){{$}}
742 ; SIMD128-NEXT: i32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
743 ; SIMD128-NEXT: return $pop[[R]]{{$}}
750 ; NO-SIMD128-NOT: i32x4
751 ; SIMD128-NEXT: .functype mul_v4i32 (v128, v128) -> (v128){{$}}
752 ; SIMD128-NEXT: i32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
753 ; SIMD128-NEXT: return $pop[[R]]{{$}}
760 ; NO-SIMD128-NOT: i32x4
761 ; SIMD128-NEXT: .functype min_s_v4i32 (v128, v128) -> (v128){{$}}
762 ; SIMD128-NEXT: i32x4.min_s $push[[R:[0-9]+]]=, $0, $1{{$}}
763 ; SIMD128-NEXT: return $pop[[R]]{{$}}
771 ; NO-SIMD128-NOT: i32x4
772 ; SIMD128-NEXT: .functype min_u_v4i32 (v128, v128) -> (v128){{$}}
773 ; SIMD128-NEXT: i32x4.min_u $push[[R:[0-9]+]]=, $0, $1{{$}}
774 ; SIMD128-NEXT: return $pop[[R]]{{$}}
782 ; NO-SIMD128-NOT: i32x4
783 ; SIMD128-NEXT: .functype max_s_v4i32 (v128, v128) -> (v128){{$}}
784 ; SIMD128-NEXT: i32x4.max_s $push[[R:[0-9]+]]=, $0, $1{{$}}
785 ; SIMD128-NEXT: return $pop[[R]]{{$}}
793 ; NO-SIMD128-NOT: i32x4
794 ; SIMD128-NEXT: .functype max_u_v4i32 (v128, v128) -> (v128){{$}}
795 ; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
796 ; SIMD128-NEXT: return $pop[[R]]{{$}}
804 ; NO-SIMD128-NOT: i32x4
805 ; SIMD128-NEXT: .functype abs_v4i32 (v128) -> (v128){{$}}
806 ; SIMD128-NEXT: i32x4.abs $push[[R:[0-9]+]]=, $0{{$}}
807 ; SIMD128-NEXT: return $pop[[R]]{{$}}
816 ; NO-SIMD128-NOT: i32x4
817 ; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}}
818 ; SIMD128-NEXT: i32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
819 ; SIMD128-NEXT: return $pop[[R]]{{$}}
826 ; NO-SIMD128-NOT: i32x4
827 ; SIMD128-NEXT: .functype shl_v4i32 (v128, i32) -> (v128){{$}}
828 ; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
829 ; SIMD128-NEXT: return $pop[[R]]{{$}}
839 ; NO-SIMD128-NOT: i32x4
840 ; SIMD128-NEXT: .functype shl_const_v4i32 (v128) -> (v128){{$}}
841 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5
842 ; SIMD128-NEXT: i32x4.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
843 ; SIMD128-NEXT: return $pop[[R]]{{$}}
850 ; NO-SIMD128-NOT: i32x4
851 ; SIMD128-NEXT: .functype shl_vec_v4i32 (v128, v128) -> (v128){{$}}
852 ; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
853 ; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
854 ; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
855 ; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
857 ; SIMD128:      i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}}
858 ; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}}
859 ; SIMD128-NEXT: i32.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
860 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}}
861 ; SIMD128-NEXT: return $pop[[R]]{{$}}
868 ; NO-SIMD128-NOT: i32x4
869 ; SIMD128-NEXT: .functype shr_s_v4i32 (v128, i32) -> (v128){{$}}
870 ; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
871 ; SIMD128-NEXT: return $pop[[R]]{{$}}
881 ; NO-SIMD128-NOT: i32x4
882 ; SIMD128-NEXT: .functype shr_s_vec_v4i32 (v128, v128) -> (v128){{$}}
883 ; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
884 ; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
885 ; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
886 ; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
888 ; SIMD128:      i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}}
889 ; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}}
890 ; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
891 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}}
892 ; SIMD128-NEXT: return $pop[[R]]{{$}}
899 ; NO-SIMD128-NOT: i32x4
900 ; SIMD128-NEXT: .functype shr_u_v4i32 (v128, i32) -> (v128){{$}}
901 ; SIMD128-NEXT: i32x4.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
902 ; SIMD128-NEXT: return $pop[[R]]{{$}}
912 ; NO-SIMD128-NOT: i32x4
913 ; SIMD128-NEXT: .functype shr_u_vec_v4i32 (v128, v128) -> (v128){{$}}
914 ; SIMD128-NEXT: i32x4.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
915 ; SIMD128-NEXT: i32x4.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
916 ; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
917 ; SIMD128-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
919 ; SIMD128:      i32x4.extract_lane $push[[L4:[0-9]+]]=, $0, 3{{$}}
920 ; SIMD128-NEXT: i32x4.extract_lane $push[[L5:[0-9]+]]=, $1, 3{{$}}
921 ; SIMD128-NEXT: i32.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
922 ; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $pop[[L7:[0-9]+]], 3, $pop[[L6]]{{$}}
923 ; SIMD128-NEXT: return $pop[[R]]{{$}}
930 ; NO-SIMD128-NOT: v128
931 ; SIMD128-NEXT: .functype and_v4i32 (v128, v128) -> (v128){{$}}
932 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
933 ; SIMD128-NEXT: return $pop[[R]]{{$}}
940 ; NO-SIMD128-NOT: v128
941 ; SIMD128-NEXT: .functype or_v4i32 (v128, v128) -> (v128){{$}}
942 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
943 ; SIMD128-NEXT: return $pop[[R]]{{$}}
950 ; NO-SIMD128-NOT: v128
951 ; SIMD128-NEXT: .functype xor_v4i32 (v128, v128) -> (v128){{$}}
952 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
953 ; SIMD128-NEXT: return $pop[[R]]{{$}}
960 ; NO-SIMD128-NOT: v128
961 ; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}}
962 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
963 ; SIMD128-NEXT: return $pop[[R]]{{$}}
970 ; NO-SIMD128-NOT: v128
971 ; SIMD128-NEXT: .functype andnot_v4i32 (v128, v128) -> (v128){{$}}
972 ; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
973 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
974 ; SIMD128-FAST-NEXT: v128.not
975 ; SIMD128-FAST-NEXT: v128.and
976 ; SIMD128-FAST-NEXT: return
984 ; NO-SIMD128-NOT: v128
985 ; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
986 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
987 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
988 ; SIMD128-FAST-NEXT: v128.not
989 ; SIMD128-FAST-NEXT: v128.and
990 ; SIMD128-FAST-NEXT: v128.and
991 ; SIMD128-FAST-NEXT: v128.or
992 ; SIMD128-FAST-NEXT: return
1002 ; NO-SIMD128-NOT: i32x4
1003 ; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
1004 ; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
1005 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1018 ; NO-SIMD128-NOT: i32x4
1019 ; SIMD128-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
1020 ; SIMD128-SLOW-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
1021 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1034 ; NO-SIMD128-NOT: i32x4
1035 ; SIMD128-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
1036 ; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
1037 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1050 ; NO-SIMD128-NOT: i32x4
1051 ; SIMD128-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
1052 ; SIMD128-SLOW-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
1053 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1069 ; NO-SIMD128-NOT: i64x2
1070 ; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}}
1071 ; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
1072 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1079 ; NO-SIMD128-NOT: i64x2
1080 ; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}}
1081 ; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
1082 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1089 ; NO-SIMD128-NOT: i64x2
1090 ; SIMD128-NEXT: .functype mul_v2i64 (v128, v128) -> (v128){{$}}
1091 ; SIMD128: i64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
1092 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1099 ; NO-SIMD128-NOT: i64x2:
1100 ; SIMD128-NEXT: .functype abs_v2i64 (v128) -> (v128){{$}}
1101 ; SIMD128-NEXT: i64x2.abs $push[[R:[0-9]+]]=, $0{{$}}
1102 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1111 ; NO-SIMD128-NOT: i64x2
1112 ; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}}
1113 ; SIMD128-NEXT: i64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
1114 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1121 ; NO-SIMD128-NOT: i64x2
1122 ; SIMD128-NEXT: .functype shl_v2i64 (v128, i32) -> (v128){{$}}
1123 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
1124 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1134 ; NO-SIMD128-NOT: i64x2
1135 ; SIMD128-NEXT: .functype shl_sext_v2i64 (v128, i32) -> (v128){{$}}
1136 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $1{{$}}
1137 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1147 ; NO-SIMD128-NOT: i64x2
1148 ; SIMD128-NEXT: .functype shl_noext_v2i64 (v128, i64) -> (v128){{$}}
1149 ; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}}
1150 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1151 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1160 ; NO-SIMD128-NOT: i64x2
1161 ; SIMD128-NEXT: .functype shl_const_v2i64 (v128) -> (v128){{$}}
1162 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}}
1163 ; SIMD128-NEXT: i64x2.shl $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1164 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1171 ; NO-SIMD128-NOT: i64x2
1172 ; SIMD128-NEXT: .functype shl_vec_v2i64 (v128, v128) -> (v128){{$}}
1173 ; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
1174 ; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
1175 ; SIMD128-NEXT: i64.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
1176 ; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
1177 ; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}}
1178 ; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}}
1179 ; SIMD128-NEXT: i64.shl $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
1180 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}}
1181 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1188 ; NO-SIMD128-NOT: i64x2
1189 ; SIMD128-NEXT: .functype shr_s_v2i64 (v128, i32) -> (v128){{$}}
1190 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
1191 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1201 ; NO-SIMD128-NOT: i64x2
1202 ; SIMD128-NEXT: .functype shr_s_sext_v2i64 (v128, i32) -> (v128){{$}}
1203 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
1204 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1214 ; NO-SIMD128-NOT: i64x2
1215 ; SIMD128-NEXT: .functype shr_s_noext_v2i64 (v128, i64) -> (v128){{$}}
1216 ; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}}
1217 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1218 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1227 ; NO-SIMD128-NOT: i64x2
1228 ; SIMD128-NEXT: .functype shr_s_const_v2i64 (v128) -> (v128){{$}}
1229 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}}
1230 ; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1231 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1238 ; NO-SIMD128-NOT: i64x2
1239 ; SIMD128-NEXT: .functype shr_s_vec_v2i64 (v128, v128) -> (v128){{$}}
1240 ; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
1241 ; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
1242 ; SIMD128-NEXT: i64.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
1243 ; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
1244 ; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}}
1245 ; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}}
1246 ; SIMD128-NEXT: i64.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
1247 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}}
1248 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1255 ; NO-SIMD128-NOT: i64x2
1256 ; SIMD128-NEXT: .functype shr_u_v2i64 (v128, i32) -> (v128){{$}}
1257 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
1258 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1268 ; NO-SIMD128-NOT: i64x2
1269 ; SIMD128-NEXT: .functype shr_u_sext_v2i64 (v128, i32) -> (v128){{$}}
1270 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
1271 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1281 ; NO-SIMD128-NOT: i64x2
1282 ; SIMD128-NEXT: .functype shr_u_noext_v2i64 (v128, i64) -> (v128){{$}}
1283 ; SIMD128-NEXT: i32.wrap_i64 $push[[L0:[0-9]+]]=, $1{{$}}
1284 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1285 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1294 ; NO-SIMD128-NOT: i64x2
1295 ; SIMD128-NEXT: .functype shr_u_const_v2i64 (v128) -> (v128){{$}}
1296 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 5{{$}}
1297 ; SIMD128-NEXT: i64x2.shr_u $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1298 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1305 ; NO-SIMD128-NOT: i64x2
1306 ; SIMD128-NEXT: .functype shr_u_vec_v2i64 (v128, v128) -> (v128){{$}}
1307 ; SIMD128-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $0, 0{{$}}
1308 ; SIMD128-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0{{$}}
1309 ; SIMD128-NEXT: i64.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
1310 ; SIMD128-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
1311 ; SIMD128-NEXT: i64x2.extract_lane $push[[L4:[0-9]+]]=, $0, 1{{$}}
1312 ; SIMD128-NEXT: i64x2.extract_lane $push[[L5:[0-9]+]]=, $1, 1{{$}}
1313 ; SIMD128-NEXT: i64.shr_u $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
1314 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L3]], 1, $pop[[L6]]{{$}}
1315 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1322 ; NO-SIMD128-NOT: v128
1323 ; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}}
1324 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
1325 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1332 ; NO-SIMD128-NOT: v128
1333 ; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}}
1334 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
1335 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1342 ; NO-SIMD128-NOT: v128
1343 ; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}}
1344 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
1345 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1352 ; NO-SIMD128-NOT: v128
1353 ; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}}
1354 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
1355 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1362 ; NO-SIMD128-NOT: v128
1363 ; SIMD128-NEXT: .functype andnot_v2i64 (v128, v128) -> (v128){{$}}
1364 ; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
1365 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1366 ; SIMD128-FAST-NEXT: v128.not
1367 ; SIMD128-FAST-NEXT: v128.and
1368 ; SIMD128-FAST-NEXT: return
1376 ; NO-SIMD128-NOT: v128
1377 ; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
1378 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
1379 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1380 ; SIMD128-FAST-NEXT: v128.not
1381 ; SIMD128-FAST-NEXT: v128.and
1382 ; SIMD128-FAST-NEXT: v128.and
1383 ; SIMD128-FAST-NEXT: v128.or
1384 ; SIMD128-FAST-NEXT: return
1394 ; NO-SIMD128-NOT: i64x2
1395 ; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
1396 ; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
1397 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1408 ; NO-SIMD128-NOT: i64x2
1409 ; SIMD128-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
1410 ; SIMD128-SLOW-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
1411 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1422 ; NO-SIMD128-NOT: i64x2
1423 ; SIMD128-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
1424 ; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
1425 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1436 ; NO-SIMD128-NOT: i64x2
1437 ; SIMD128-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
1438 ; SIMD128-SLOW-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
1439 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
1453 ; NO-SIMD128-NOT: f32x4
1454 ; SIMD128-NEXT: .functype neg_v4f32 (v128) -> (v128){{$}}
1455 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
1456 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1464 ; NO-SIMD128-NOT: f32x4
1465 ; SIMD128-NEXT: .functype abs_v4f32 (v128) -> (v128){{$}}
1466 ; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}}
1467 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1475 ; NO-SIMD128-NOT: f32x4
1476 ; SIMD128-NEXT: .functype min_unordered_v4f32 (v128) -> (v128){{$}}
1477 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}}
1478 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1479 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1488 ; NO-SIMD128-NOT: f32x4
1489 ; SIMD128-NEXT: .functype max_unordered_v4f32 (v128) -> (v128){{$}}
1490 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
1491 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1492 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1501 ; NO-SIMD128-NOT: f32x4
1502 ; SIMD128-NEXT: .functype min_ordered_v4f32 (v128) -> (v128){{$}}
1503 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}}
1504 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1505 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1514 ; NO-SIMD128-NOT: f32x4
1515 ; SIMD128-NEXT: .functype max_ordered_v4f32 (v128) -> (v128){{$}}
1516 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}}
1517 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1518 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1527 ; NO-SIMD128-NOT: f32x4
1528 ; SIMD128-NEXT: .functype min_intrinsic_v4f32 (v128, v128) -> (v128){{$}}
1529 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}}
1530 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1538 ; NO-SIMD128-NOT: f32x4
1539 ; SIMD128-NEXT: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}}
1540 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $1{{$}}
1541 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1549 ; NO-SIMD128-NOT: f32x4
1550 ; SIMD128-NEXT: .functype max_intrinsic_v4f32 (v128, v128) -> (v128){{$}}
1551 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}}
1552 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1560 ; NO-SIMD128-NOT: f32x4
1561 ; SIMD128-NEXT: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128){{$}}
1562 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $1{{$}}
1563 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1571 ; NO-SIMD128-NOT: f32x4
1572 ; SIMD128-NEXT: .functype min_const_intrinsic_v4f32 () -> (v128){{$}}
1573 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2{{$}}
1574 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1584 ; NO-SIMD128-NOT: f32x4
1585 ; SIMD128-NEXT: .functype max_const_intrinsic_v4f32 () -> (v128){{$}}
1586 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.5p5, 0x1.5p5, 0x1.5p5, 0x1.5p5{{$}}
1587 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1597 ; NO-SIMD128-NOT: f32x4
1598 ; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
1599 ; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1600 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1608 ; NO-SIMD128-NOT: f32x4
1609 ; SIMD128-NEXT: .functype pmin_int_v4f32 (v128, v128) -> (v128){{$}}
1610 ; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1611 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1621 ; NO-SIMD128-NOT: f32x4
1622 ; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
1623 ; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1624 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1632 ; NO-SIMD128-NOT: f32x4
1633 ; SIMD128-NEXT: .functype pmax_int_v4f32 (v128, v128) -> (v128){{$}}
1634 ; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1635 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1645 ; NO-SIMD128-NOT: f32x4
1646 ; SIMD128-NEXT: .functype add_v4f32 (v128, v128) -> (v128){{$}}
1647 ; SIMD128-NEXT: f32x4.add $push[[R:[0-9]+]]=, $0, $1{{$}}
1648 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1655 ; NO-SIMD128-NOT: f32x4
1656 ; SIMD128-NEXT: .functype sub_v4f32 (v128, v128) -> (v128){{$}}
1657 ; SIMD128-NEXT: f32x4.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
1658 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1665 ; NO-SIMD128-NOT: f32x4
1666 ; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}}
1667 ; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}}
1668 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1675 ; NO-SIMD128-NOT: f32x4
1676 ; SIMD128-NEXT: .functype mul_v4f32 (v128, v128) -> (v128){{$}}
1677 ; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
1678 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1685 ; NO-SIMD128-NOT: f32x4
1686 ; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}}
1687 ; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}}
1688 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1699 ; NO-SIMD128-NOT: f64x2
1700 ; SIMD128-NEXT: .functype neg_v2f64 (v128) -> (v128){{$}}
1701 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
1702 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1710 ; NO-SIMD128-NOT: f64x2
1711 ; SIMD128-NEXT: .functype abs_v2f64 (v128) -> (v128){{$}}
1712 ; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}}
1713 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1721 ; NO-SIMD128-NOT: f64x2
1722 ; SIMD128-NEXT: .functype min_unordered_v2f64 (v128) -> (v128){{$}}
1723 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}}
1724 ; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1725 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1734 ; NO-SIMD128-NOT: f64x2
1735 ; SIMD128-NEXT: .functype max_unordered_v2f64 (v128) -> (v128){{$}}
1736 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}}
1737 ; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1738 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1747 ; NO-SIMD128-NOT: f64x2
1748 ; SIMD128-NEXT: .functype min_ordered_v2f64 (v128) -> (v128){{$}}
1749 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}}
1750 ; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1751 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1760 ; NO-SIMD128-NOT: f64x2
1761 ; SIMD128-NEXT: .functype max_ordered_v2f64 (v128) -> (v128){{$}}
1762 ; SIMD128-NEXT: v128.const $push[[L0:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}}
1763 ; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}}
1764 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1773 ; NO-SIMD128-NOT: f64x2
1774 ; SIMD128-NEXT: .functype min_intrinsic_v2f64 (v128, v128) -> (v128){{$}}
1775 ; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $1{{$}}
1776 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1784 ; NO-SIMD128-NOT: f64x2
1785 ; SIMD128-NEXT: .functype max_intrinsic_v2f64 (v128, v128) -> (v128){{$}}
1786 ; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $1{{$}}
1787 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1795 ; NO-SIMD128-NOT: f64x2
1796 ; SIMD128-NEXT: .functype min_const_intrinsic_v2f64 () -> (v128){{$}}
1797 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.4p2, 0x1.4p2{{$}}
1798 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1808 ; NO-SIMD128-NOT: f64x2
1809 ; SIMD128-NEXT: .functype max_const_intrinsic_v2f64 () -> (v128){{$}}
1810 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.5p5, 0x1.5p5{{$}}
1811 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1821 ; NO-SIMD128-NOT: f64x2
1822 ; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
1823 ; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1824 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1832 ; NO-SIMD128-NOT: f64x2
1833 ; SIMD128-NEXT: .functype pmin_int_v2f64 (v128, v128) -> (v128){{$}}
1834 ; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
1835 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1845 ; NO-SIMD128-NOT: f64x2
1846 ; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
1847 ; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1848 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1856 ; NO-SIMD128-NOT: f64x2
1857 ; SIMD128-NEXT: .functype pmax_int_v2f64 (v128, v128) -> (v128){{$}}
1858 ; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
1859 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1869 ; NO-SIMD128-NOT: f64x2
1870 ; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}}
1871 ; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
1872 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1879 ; NO-SIMD128-NOT: f64x2
1880 ; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}}
1881 ; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
1882 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1889 ; NO-SIMD128-NOT: f64x2
1890 ; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}}
1891 ; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}}
1892 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1899 ; NO-SIMD128-NOT: f64x2
1900 ; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}}
1901 ; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
1902 ; SIMD128-NEXT: return $pop[[R]]{{$}}
1909 ; NO-SIMD128-NOT: f64x2
1910 ; SIMD128-NEXT: .functype sqrt_v2f64 (v128) -> (v128){{$}}
1911 ; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}}
1912 ; SIMD128-NEXT: return $pop[[R]]{{$}}