Lines Matching refs:ImplicitOp

1069                                   bool &isKill, MachineOperand &ImplicitOp,  in classifyLEAReg()  argument
1097 ImplicitOp = Src; in classifyLEAReg()
1098 ImplicitOp.setImplicit(); in classifyLEAReg()
1371 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1373 ImplicitOp, LV, LIS)) in convertToThreeAddress()
1384 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1385 MIB.add(ImplicitOp); in convertToThreeAddress()
1406 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1408 ImplicitOp, LV, LIS)) in convertToThreeAddress()
1415 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1416 MIB.add(ImplicitOp); in convertToThreeAddress()
1428 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1430 ImplicitOp, LV, LIS)) in convertToThreeAddress()
1436 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1437 MIB.add(ImplicitOp); in convertToThreeAddress()
1469 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1477 ImplicitOp, LV, LIS)) in convertToThreeAddress()
1482 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1483 MIB.add(ImplicitOp); in convertToThreeAddress()
1516 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1518 ImplicitOp, LV, LIS)) in convertToThreeAddress()
1524 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1525 MIB.add(ImplicitOp); in convertToThreeAddress()
1556 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); in convertToThreeAddress() local
1558 ImplicitOp, LV, LIS)) in convertToThreeAddress()
1564 if (ImplicitOp.getReg() != 0) in convertToThreeAddress()
1565 MIB.add(ImplicitOp); in convertToThreeAddress()