Lines Matching refs:PPC
99 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
103 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
104 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
105 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
106 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
107 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
108 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
109 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
110 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
111 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
114 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; in PPCRegisterInfo()
115 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; in PPCRegisterInfo()
116 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; in PPCRegisterInfo()
117 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; in PPCRegisterInfo()
118 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; in PPCRegisterInfo()
119 ImmToIdxMap[PPC::LQ] = PPC::LQX_PSEUDO; in PPCRegisterInfo()
120 ImmToIdxMap[PPC::STQ] = PPC::STQX_PSEUDO; in PPCRegisterInfo()
123 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX; in PPCRegisterInfo()
124 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX; in PPCRegisterInfo()
125 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX; in PPCRegisterInfo()
126 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX; in PPCRegisterInfo()
127 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX; in PPCRegisterInfo()
128 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX; in PPCRegisterInfo()
129 ImmToIdxMap[PPC::LXV] = PPC::LXVX; in PPCRegisterInfo()
130 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; in PPCRegisterInfo()
131 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX; in PPCRegisterInfo()
132 ImmToIdxMap[PPC::STXV] = PPC::STXVX; in PPCRegisterInfo()
133 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; in PPCRegisterInfo()
134 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; in PPCRegisterInfo()
137 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX; in PPCRegisterInfo()
138 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX; in PPCRegisterInfo()
139 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX; in PPCRegisterInfo()
140 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX; in PPCRegisterInfo()
143 ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8; in PPCRegisterInfo()
144 ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8; in PPCRegisterInfo()
145 ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8; in PPCRegisterInfo()
146 ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8; in PPCRegisterInfo()
147 ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX; in PPCRegisterInfo()
148 ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX; in PPCRegisterInfo()
150 ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8; in PPCRegisterInfo()
151 ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8; in PPCRegisterInfo()
152 ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8; in PPCRegisterInfo()
154 ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX; in PPCRegisterInfo()
155 ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX; in PPCRegisterInfo()
156 ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX; in PPCRegisterInfo()
157 ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX; in PPCRegisterInfo()
158 ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX; in PPCRegisterInfo()
160 ImmToIdxMap[PPC::LXVP] = PPC::LXVPX; in PPCRegisterInfo()
161 ImmToIdxMap[PPC::STXVP] = PPC::STXVPX; in PPCRegisterInfo()
162 ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX; in PPCRegisterInfo()
163 ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX; in PPCRegisterInfo()
175 return &PPC::G8RC_NOX0RegClass; in getPointerRegClass()
176 return &PPC::GPRC_NOR0RegClass; in getPointerRegClass()
180 return &PPC::G8RCRegClass; in getPointerRegClass()
181 return &PPC::GPRCRegClass; in getPointerRegClass()
212 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) && in getCalleeSavedRegs()
330 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) in adjustStackMapLiveOutMask()
341 markSuperRegs(Reserved, PPC::ZERO); in getReservedRegs()
345 markSuperRegs(Reserved, PPC::FP); in getReservedRegs()
349 markSuperRegs(Reserved, PPC::BP); in getReservedRegs()
353 markSuperRegs(Reserved, PPC::CTR); in getReservedRegs()
354 markSuperRegs(Reserved, PPC::CTR8); in getReservedRegs()
356 markSuperRegs(Reserved, PPC::R1); in getReservedRegs()
357 markSuperRegs(Reserved, PPC::LR); in getReservedRegs()
358 markSuperRegs(Reserved, PPC::LR8); in getReservedRegs()
359 markSuperRegs(Reserved, PPC::RM); in getReservedRegs()
361 markSuperRegs(Reserved, PPC::VRSAVE); in getReservedRegs()
372 markSuperRegs(Reserved, PPC::R2); // System-reserved register in getReservedRegs()
373 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register in getReservedRegs()
379 markSuperRegs(Reserved, PPC::R2); // System-reserved register in getReservedRegs()
383 markSuperRegs(Reserved, PPC::R13); in getReservedRegs()
386 markSuperRegs(Reserved, PPC::R31); in getReservedRegs()
391 markSuperRegs(Reserved, PPC::R29); in getReservedRegs()
393 markSuperRegs(Reserved, PPC::R30); in getReservedRegs()
397 markSuperRegs(Reserved, PPC::R30); in getReservedRegs()
401 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), in getReservedRegs()
402 IE = PPC::VRRCRegClass.end(); I != IE; ++I) in getReservedRegs()
432 return PhysReg != PPC::R1 && PhysReg != PPC::X1; in isAsmClobberable()
498 if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) { in requiresFrameIndexScavenging()
572 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && in getRegAllocationHints()
577 if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31) in getRegAllocationHints()
582 case PPC::BUILD_UACC: { in getRegAllocationHints()
585 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && in getRegAllocationHints()
588 assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) && in getRegAllocationHints()
590 Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0); in getRegAllocationHints()
608 case PPC::G8RC_NOX0RegClassID: in getRegPressureLimit()
609 case PPC::GPRC_NOR0RegClassID: in getRegPressureLimit()
610 case PPC::SPERCRegClassID: in getRegPressureLimit()
611 case PPC::G8RCRegClassID: in getRegPressureLimit()
612 case PPC::GPRCRegClassID: { in getRegPressureLimit()
616 case PPC::F4RCRegClassID: in getRegPressureLimit()
617 case PPC::F8RCRegClassID: in getRegPressureLimit()
618 case PPC::VSLRCRegClassID: in getRegPressureLimit()
620 case PPC::VFRCRegClassID: in getRegPressureLimit()
621 case PPC::VRRCRegClassID: { in getRegPressureLimit()
629 case PPC::VSFRCRegClassID: in getRegPressureLimit()
630 case PPC::VSSRCRegClassID: in getRegPressureLimit()
631 case PPC::VSRCRegClassID: { in getRegPressureLimit()
639 case PPC::CRRCRegClassID: in getRegPressureLimit()
659 RC == &PPC::G8RCRegClass) { in getLargestLegalSuperClass()
661 return &PPC::SPILLTOVSRRCRegClass; in getLargestLegalSuperClass()
663 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills) in getLargestLegalSuperClass()
672 case PPC::VSSRCRegClassID: in getLargestLegalSuperClass()
674 case PPC::VSFRCRegClassID: in getLargestLegalSuperClass()
675 case PPC::VSRCRegClassID: in getLargestLegalSuperClass()
677 case PPC::VSRpRCRegClassID: in getLargestLegalSuperClass()
679 case PPC::ACCRCRegClassID: in getLargestLegalSuperClass()
680 case PPC::UACCRCRegClassID: in getLargestLegalSuperClass()
723 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerDynamicAlloc()
724 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc()
733 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
735 .addReg(PPC::X1) in lowerDynamicAlloc()
737 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
738 .addReg(PPC::X1) in lowerDynamicAlloc()
741 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
743 .addReg(PPC::R1) in lowerDynamicAlloc()
745 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
746 .addReg(PPC::R1) in lowerDynamicAlloc()
789 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in prepareDynamicAlloca()
790 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca()
794 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer) in prepareDynamicAlloca()
795 .addReg(PPC::X31) in prepareDynamicAlloca()
798 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
799 .addReg(PPC::R31) in prepareDynamicAlloca()
802 BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer) in prepareDynamicAlloca()
804 .addReg(PPC::X1); in prepareDynamicAlloca()
806 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer) in prepareDynamicAlloca()
808 .addReg(PPC::R1); in prepareDynamicAlloca()
818 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in prepareDynamicAlloca()
823 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in prepareDynamicAlloca()
835 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in prepareDynamicAlloca()
840 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in prepareDynamicAlloca()
865 const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR); in lowerPrepareProbedAlloca()
906 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), in lowerDynamicAreaOffset()
932 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRSpilling()
933 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling()
940 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRSpilling()
945 if (SrcReg != PPC::CR0) { in lowerCRSpilling()
950 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) in lowerCRSpilling()
957 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRSpilling()
977 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRRestore()
978 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore()
985 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
990 if (DestReg != PPC::CR0) { in lowerCRRestore()
996 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) in lowerCRRestore()
1001 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) in lowerCRRestore()
1021 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRBitSpilling()
1022 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitSpilling()
1057 case PPC::CRUNSET: in lowerCRBitSpilling()
1058 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg) in lowerCRBitSpilling()
1062 case PPC::CRSET: in lowerCRBitSpilling()
1063 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg) in lowerCRBitSpilling()
1073 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg) in lowerCRBitSpilling()
1083 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT || in lowerCRBitSpilling()
1084 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT || in lowerCRBitSpilling()
1085 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT || in lowerCRBitSpilling()
1086 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) { in lowerCRBitSpilling()
1087 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg) in lowerCRBitSpilling()
1098 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRBitSpilling()
1109 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) in lowerCRBitSpilling()
1114 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRBitSpilling()
1122 Ins->setDesc(TII.get(PPC::UNENCODED_NOP)); in lowerCRBitSpilling()
1139 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRBitRestore()
1140 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitRestore()
1147 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
1153 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) in lowerCRBitRestore()
1158 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) in lowerCRBitRestore()
1165 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), in lowerCRBitRestore()
1183 std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc"; in emitAccCopyInfo()
1184 std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc"; in emitAccCopyInfo()
1214 Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2 in spillRegPairs()
1215 : PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2; in spillRegPairs()
1216 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) in spillRegPairs()
1220 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) in spillRegPairs()
1225 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) in spillRegPairs()
1229 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV)) in spillRegPairs()
1273 bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg); in lowerACCSpilling()
1275 PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; in lowerACCSpilling()
1285 BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg); in lowerACCSpilling()
1290 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) in lowerACCSpilling()
1293 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) in lowerACCSpilling()
1298 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg); in lowerACCSpilling()
1318 bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg); in lowerACCRestore()
1320 PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; in lowerACCRestore()
1327 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg), in lowerACCRestore()
1329 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1), in lowerACCRestore()
1332 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg); in lowerACCRestore()
1351 Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2; in lowerQuadwordSpilling()
1354 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) in lowerQuadwordSpilling()
1357 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) in lowerQuadwordSpilling()
1379 Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2; in lowerQuadwordRestore()
1382 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg), FrameIndex, in lowerQuadwordRestore()
1384 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg + 1), FrameIndex, in lowerQuadwordRestore()
1401 if (PPC::CR2 <= Reg && Reg <= PPC::CR4) { in hasReservedSpillSlot()
1413 case PPC::LWA: in offsetMinAlignForOpcode()
1414 case PPC::LWA_32: in offsetMinAlignForOpcode()
1415 case PPC::LD: in offsetMinAlignForOpcode()
1416 case PPC::LDU: in offsetMinAlignForOpcode()
1417 case PPC::STD: in offsetMinAlignForOpcode()
1418 case PPC::STDU: in offsetMinAlignForOpcode()
1419 case PPC::DFLOADf32: in offsetMinAlignForOpcode()
1420 case PPC::DFLOADf64: in offsetMinAlignForOpcode()
1421 case PPC::DFSTOREf32: in offsetMinAlignForOpcode()
1422 case PPC::DFSTOREf64: in offsetMinAlignForOpcode()
1423 case PPC::LXSD: in offsetMinAlignForOpcode()
1424 case PPC::LXSSP: in offsetMinAlignForOpcode()
1425 case PPC::STXSD: in offsetMinAlignForOpcode()
1426 case PPC::STXSSP: in offsetMinAlignForOpcode()
1427 case PPC::STQ: in offsetMinAlignForOpcode()
1429 case PPC::EVLDD: in offsetMinAlignForOpcode()
1430 case PPC::EVSTDD: in offsetMinAlignForOpcode()
1432 case PPC::LXV: in offsetMinAlignForOpcode()
1433 case PPC::STXV: in offsetMinAlignForOpcode()
1434 case PPC::LQ: in offsetMinAlignForOpcode()
1435 case PPC::LXVP: in offsetMinAlignForOpcode()
1436 case PPC::STXVP: in offsetMinAlignForOpcode()
1492 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) { in eliminateFrameIndex()
1499 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { in eliminateFrameIndex()
1505 (OpC == PPC::PREPARE_PROBED_ALLOCA_64 || in eliminateFrameIndex()
1506 OpC == PPC::PREPARE_PROBED_ALLOCA_32 || in eliminateFrameIndex()
1507 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 || in eliminateFrameIndex()
1508 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) { in eliminateFrameIndex()
1514 if (OpC == PPC::SPILL_CR) { in eliminateFrameIndex()
1517 } else if (OpC == PPC::RESTORE_CR) { in eliminateFrameIndex()
1520 } else if (OpC == PPC::SPILL_CRBIT) { in eliminateFrameIndex()
1523 } else if (OpC == PPC::RESTORE_CRBIT) { in eliminateFrameIndex()
1526 } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) { in eliminateFrameIndex()
1529 } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) { in eliminateFrameIndex()
1532 } else if (OpC == PPC::STXVP && DisableAutoPairedVecSt) { in eliminateFrameIndex()
1535 } else if (OpC == PPC::SPILL_QUADWORD) { in eliminateFrameIndex()
1538 } else if (OpC == PPC::RESTORE_QUADWORD) { in eliminateFrameIndex()
1569 if ((OpC == PPC::LXVP || OpC == PPC::STXVP) && in eliminateFrameIndex()
1572 unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP; in eliminateFrameIndex()
1583 assert(OpC != PPC::DBG_VALUE && in eliminateFrameIndex()
1587 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ? in eliminateFrameIndex()
1604 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in eliminateFrameIndex()
1605 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in eliminateFrameIndex()
1613 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1616 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) in eliminateFrameIndex()
1618 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1652 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { in eliminateFrameIndex()
1654 Register NewReg = MF.getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); in eliminateFrameIndex()
1655 BuildMI(MBB, II, dl, TII.get(PPC::ADD8), NewReg) in eliminateFrameIndex()
1658 MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); in eliminateFrameIndex()
1668 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; in getFrameRegister()
1670 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; in getFrameRegister()
1679 return PPC::X30; in getBaseRegister()
1682 return PPC::R29; in getBaseRegister()
1684 return PPC::R30; in getBaseRegister()
1721 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1751 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
1810 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm in isFrameOffsetLegal()