Lines Matching refs:AVR
40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
49 setStackPointerRegisterToSaveRestore(AVR::SP); in AVRTargetLowering()
912 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { in isLegalAddressingMode()
943 if (AVR::isProgramMemoryAccess(LD)) { in getPreIndexedAddressParts()
949 if (AVR::isProgramMemoryAccess(ST)) { in getPreIndexedAddressParts()
1000 if (AVR::isProgramMemoryAccess(ST)) { in getPostIndexedAddressParts()
1047 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1048 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1049 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1050 static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1051 AVR::R22, AVR::R21, AVR::R20};
1053 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1054 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1055 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1056 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1057 static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1058 AVR::R24R23, AVR::R23R22,
1059 AVR::R22R21, AVR::R21R20};
1239 RC = &AVR::GPR8RegClass; in LowerFormalArguments()
1241 RC = &AVR::DREGSRegClass; in LowerFormalArguments()
1421 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), in LowerCall()
1604 case AVR::Lsl8: in insertShift()
1605 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd in insertShift()
1606 RC = &AVR::GPR8RegClass; in insertShift()
1609 case AVR::Lsl16: in insertShift()
1610 Opc = AVR::LSLWRd; in insertShift()
1611 RC = &AVR::DREGSRegClass; in insertShift()
1613 case AVR::Asr8: in insertShift()
1614 Opc = AVR::ASRRd; in insertShift()
1615 RC = &AVR::GPR8RegClass; in insertShift()
1617 case AVR::Asr16: in insertShift()
1618 Opc = AVR::ASRWRd; in insertShift()
1619 RC = &AVR::DREGSRegClass; in insertShift()
1621 case AVR::Lsr8: in insertShift()
1622 Opc = AVR::LSRRd; in insertShift()
1623 RC = &AVR::GPR8RegClass; in insertShift()
1625 case AVR::Lsr16: in insertShift()
1626 Opc = AVR::LSRWRd; in insertShift()
1627 RC = &AVR::DREGSRegClass; in insertShift()
1629 case AVR::Rol8: in insertShift()
1630 Opc = AVR::ROLBRd; in insertShift()
1631 RC = &AVR::GPR8RegClass; in insertShift()
1633 case AVR::Rol16: in insertShift()
1634 Opc = AVR::ROLWRd; in insertShift()
1635 RC = &AVR::DREGSRegClass; in insertShift()
1637 case AVR::Ror8: in insertShift()
1638 Opc = AVR::RORBRd; in insertShift()
1639 RC = &AVR::GPR8RegClass; in insertShift()
1641 case AVR::Ror16: in insertShift()
1642 Opc = AVR::RORWRd; in insertShift()
1643 RC = &AVR::DREGSRegClass; in insertShift()
1676 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass); in insertShift()
1677 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass); in insertShift()
1686 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB); in insertShift()
1700 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
1705 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg) in insertShift()
1710 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) in insertShift()
1716 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg); in insertShift()
1717 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB); in insertShift()
1724 if (I->getOpcode() == AVR::COPY) { in isCopyMulResult()
1726 return (SrcReg == AVR::R0 || SrcReg == AVR::R1); in isCopyMulResult()
1744 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) in insertMul()
1745 .addReg(AVR::R1) in insertMul()
1746 .addReg(AVR::R1); in insertMul()
1755 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY)) in insertCopyR1()
1757 .addReg(AVR::R1); in insertCopyR1()
1769 const Register SCRATCH_REGISTER = AVR::R0; in insertAtomicArithmeticOp()
1782 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass; in insertAtomicArithmeticOp()
1783 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr; in insertAtomicArithmeticOp()
1784 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr; in insertAtomicArithmeticOp()
1787 BuildMI(*BB, I, dl, TII.get(AVR::INRdA), SCRATCH_REGISTER) in insertAtomicArithmeticOp()
1789 BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7); in insertAtomicArithmeticOp()
1807 BuildMI(*BB, I, dl, TII.get(AVR::OUTARr)) in insertAtomicArithmeticOp()
1824 case AVR::Lsl8: in EmitInstrWithCustomInserter()
1825 case AVR::Lsl16: in EmitInstrWithCustomInserter()
1826 case AVR::Lsr8: in EmitInstrWithCustomInserter()
1827 case AVR::Lsr16: in EmitInstrWithCustomInserter()
1828 case AVR::Rol8: in EmitInstrWithCustomInserter()
1829 case AVR::Rol16: in EmitInstrWithCustomInserter()
1830 case AVR::Ror8: in EmitInstrWithCustomInserter()
1831 case AVR::Ror16: in EmitInstrWithCustomInserter()
1832 case AVR::Asr8: in EmitInstrWithCustomInserter()
1833 case AVR::Asr16: in EmitInstrWithCustomInserter()
1835 case AVR::MULRdRr: in EmitInstrWithCustomInserter()
1836 case AVR::MULSRdRr: in EmitInstrWithCustomInserter()
1838 case AVR::CopyR1: in EmitInstrWithCustomInserter()
1840 case AVR::AtomicLoadAdd8: in EmitInstrWithCustomInserter()
1841 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8); in EmitInstrWithCustomInserter()
1842 case AVR::AtomicLoadAdd16: in EmitInstrWithCustomInserter()
1843 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16); in EmitInstrWithCustomInserter()
1844 case AVR::AtomicLoadSub8: in EmitInstrWithCustomInserter()
1845 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8); in EmitInstrWithCustomInserter()
1846 case AVR::AtomicLoadSub16: in EmitInstrWithCustomInserter()
1847 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16); in EmitInstrWithCustomInserter()
1848 case AVR::AtomicLoadAnd8: in EmitInstrWithCustomInserter()
1849 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8); in EmitInstrWithCustomInserter()
1850 case AVR::AtomicLoadAnd16: in EmitInstrWithCustomInserter()
1851 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16); in EmitInstrWithCustomInserter()
1852 case AVR::AtomicLoadOr8: in EmitInstrWithCustomInserter()
1853 return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8); in EmitInstrWithCustomInserter()
1854 case AVR::AtomicLoadOr16: in EmitInstrWithCustomInserter()
1855 return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16); in EmitInstrWithCustomInserter()
1856 case AVR::AtomicLoadXor8: in EmitInstrWithCustomInserter()
1857 return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8); in EmitInstrWithCustomInserter()
1858 case AVR::AtomicLoadXor16: in EmitInstrWithCustomInserter()
1859 return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16); in EmitInstrWithCustomInserter()
1862 assert((Opc == AVR::Select16 || Opc == AVR::Select8) && in EmitInstrWithCustomInserter()
1885 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough); in EmitInstrWithCustomInserter()
1908 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); in EmitInstrWithCustomInserter()
1913 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); in EmitInstrWithCustomInserter()
1917 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), in EmitInstrWithCustomInserter()
2110 return std::make_pair(0U, &AVR::LD8loRegClass); in getRegForInlineAsmConstraint()
2112 return std::make_pair(0U, &AVR::DREGSLD8loRegClass); in getRegForInlineAsmConstraint()
2116 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); in getRegForInlineAsmConstraint()
2120 return std::make_pair(0U, &AVR::LD8RegClass); in getRegForInlineAsmConstraint()
2122 return std::make_pair(0U, &AVR::DLDREGSRegClass); in getRegForInlineAsmConstraint()
2126 return std::make_pair(0U, &AVR::GPR8loRegClass); in getRegForInlineAsmConstraint()
2128 return std::make_pair(0U, &AVR::DREGSloRegClass); in getRegForInlineAsmConstraint()
2132 return std::make_pair(0U, &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2135 return std::make_pair(0U, &AVR::GPRSPRegClass); in getRegForInlineAsmConstraint()
2138 return std::make_pair(0U, &AVR::GPR8RegClass); in getRegForInlineAsmConstraint()
2140 return std::make_pair(0U, &AVR::DREGSRegClass); in getRegForInlineAsmConstraint()
2144 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); in getRegForInlineAsmConstraint()
2148 return std::make_pair(0U, &AVR::IWREGSRegClass); in getRegForInlineAsmConstraint()
2153 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2158 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2163 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2287 .Case("r0", AVR::R0) in getRegisterByName()
2288 .Case("r1", AVR::R1) in getRegisterByName()
2292 .Case("r0", AVR::R1R0) in getRegisterByName()
2293 .Case("sp", AVR::SP) in getRegisterByName()