Lines Matching refs:RegSpc
533 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, in GetDSubRegs() argument
536 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { in GetDSubRegs()
541 } else if (RegSpc == SingleHighQSpc) { in GetDSubRegs()
546 } else if (RegSpc == SingleHighTSpc) { in GetDSubRegs()
551 } else if (RegSpc == EvenDblSpc) { in GetDSubRegs()
557 assert(RegSpc == OddDblSpc && "unknown register spacing"); in GetDSubRegs()
574 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVLD() local
596 if (RegSpc == EvenDblSpc) { in ExpandVLD()
599 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); in ExpandVLD()
608 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVLD()
659 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || in ExpandVLD()
660 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || in ExpandVLD()
661 RegSpc == SingleHighTSpc) in ExpandVLD()
695 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVST() local
737 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVST()
771 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandLaneOp() local
783 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); in ExpandLaneOp()
784 if (RegSpc == EvenDblSpc && Lane >= RegElts) { in ExpandLaneOp()
785 RegSpc = OddDblSpc; in ExpandLaneOp()
796 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()
819 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()