605     MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
609     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
611       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
613       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
615       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
797     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
799       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
801       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
803       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
997           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1004           .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1040     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1116       CLRM.addReg(R, RegState::Define);  in CMSEClearGPRegs()
1117     CLRM.addReg(ARM::APSR, RegState::Define);  in CMSEClearGPRegs()
1118     CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit);  in CMSEClearGPRegs()
1313         VSCCLRM.addReg(ARM::S0 + Start, RegState::Define);  in CMSEClearFPRegsV81()
1314       VSCCLRM.addReg(ARM::VPR, RegState::Define);  in CMSEClearFPRegsV81()
1324       VSCCLRM.addReg(ARM::S0 + Start, RegState::Define);  in CMSEClearFPRegsV81()
1325     VSCCLRM.addReg(ARM::VPR, RegState::Define);  in CMSEClearFPRegsV81()
1372               .addReg(SaveReg1, RegState::Define)  in CMSESaveClearFPRegsV8()
1373               .addReg(SaveReg2, RegState::Define)  in CMSESaveClearFPRegsV8()
1559               .addReg(SaveReg1, RegState::Define)  in CMSERestoreFPRegsV8()
1560               .addReg(SaveReg2, RegState::Define)  in CMSERestoreFPRegsV8()
1613                        .addReg(ScratchReg, RegState::Define)  in CMSERestoreFPRegsV8()
1631                          .addReg(ARM::S0, RegState::Define)  in CMSERestoreFPRegsV8()
1683           .addReg(ARM::VPR, RegState::Define);  in CMSERestoreFPRegsV81()
1710       VPOP.addReg(Reg, RegState::Define);  in CMSERestoreFPRegsV81()
1888   addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);  in ExpandCMP_SWAP_64()
2023       PopMIB.addReg(ARM::R4 + R, RegState::Define);  in CMSEPopCalleeSaves()
2031       PopMIB2.addReg(ARM::R4 + R, RegState::Define);  in CMSEPopCalleeSaves()
2038       PopMIB.addReg(Reg, RegState::Define);  in CMSEPopCalleeSaves()
2090                       RegState::Define |  in ExpandMI()
2263             .addReg(ARM::CPSR, RegState::Define)  in ExpandMI()
2465           .addReg(ARM::CPSR, RegState::Define);  in ExpandMI()
2538               .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2597             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2638         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2689       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
2690         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
3086             .addReg(ARM::SP, RegState::Define)  in ExpandMI()
3124                       Opcode == ARM::LOADDUAL ? RegState::Define : 0)  in ExpandMI()
3126                       Opcode == ARM::LOADDUAL ? RegState::Define : 0);  in ExpandMI()