Lines Matching refs:TmpOffsetVGPR

1320   Register TmpOffsetVGPR;  in buildSpillLoadStore()  local
1346           .addReg(TmpOffsetVGPR);  in buildSpillLoadStore()
1349       assert(TmpOffsetVGPR);  in buildSpillLoadStore()
1388         TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);  in buildSpillLoadStore()
1393             TmpOffsetVGPR = Reg;  in buildSpillLoadStore()
1399       assert(TmpOffsetVGPR);  in buildSpillLoadStore()
1430       MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, Offset);  in buildSpillLoadStore()
1472     if (UseVGPROffset && TmpOffsetVGPR == TmpIntermediateVGPR) {  in buildSpillLoadStore()
1479       MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, MaterializedOffset);  in buildSpillLoadStore()
1570       if (!TmpOffsetVGPR) {  in buildSpillLoadStore()
1571         TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);  in buildSpillLoadStore()
1572         RS->setRegUsed(TmpOffsetVGPR);  in buildSpillLoadStore()
1588       MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR));  in buildSpillLoadStore()