Lines Matching refs:SB
1636 void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, in buildVGPRSpillLoadStore() argument
1640 MachineFrameInfo &FrameInfo = SB.MF.getFrameInfo(); in buildVGPRSpillLoadStore()
1644 FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(SB.MF) in buildVGPRSpillLoadStore()
1646 : getFrameRegister(SB.MF); in buildVGPRSpillLoadStore()
1649 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SB.MF, Index); in buildVGPRSpillLoadStore()
1650 MachineMemOperand *MMO = SB.MF.getMachineMemOperand( in buildVGPRSpillLoadStore()
1652 SB.EltSize, Alignment); in buildVGPRSpillLoadStore()
1657 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false, in buildVGPRSpillLoadStore()
1658 FrameReg, Offset * SB.EltSize, MMO, SB.RS); in buildVGPRSpillLoadStore()
1662 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill, in buildVGPRSpillLoadStore()
1663 FrameReg, Offset * SB.EltSize, MMO, SB.RS); in buildVGPRSpillLoadStore()
1665 SB.MFI.addToSpilledVGPRs(1); in buildVGPRSpillLoadStore()
1674 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR() local
1676 ArrayRef<SpilledReg> VGPRSpills = SB.MFI.getSGPRToVGPRSpills(Index); in spillSGPR()
1681 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() && in spillSGPR()
1682 SB.SuperReg != SB.MFI.getFrameOffsetReg())); in spillSGPR()
1686 assert(SB.NumSubRegs == VGPRSpills.size() && in spillSGPR()
1689 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in spillSGPR()
1691 SB.NumSubRegs == 1 in spillSGPR()
1692 ? SB.SuperReg in spillSGPR()
1693 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillSGPR()
1696 bool UseKill = SB.IsKill && i == SB.NumSubRegs - 1; in spillSGPR()
1700 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in spillSGPR()
1701 SB.TII.get(AMDGPU::V_WRITELANE_B32), Spill.VGPR) in spillSGPR()
1712 if (i == 0 && SB.NumSubRegs > 1) { in spillSGPR()
1715 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1718 if (SB.NumSubRegs > 1) in spillSGPR()
1719 MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit); in spillSGPR()
1726 SB.prepare(); in spillSGPR()
1729 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillSGPR()
1732 auto PVD = SB.getPerVGPRData(); in spillSGPR()
1739 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillSGPR()
1742 SB.NumSubRegs == 1 in spillSGPR()
1743 ? SB.SuperReg in spillSGPR()
1744 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillSGPR()
1747 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillSGPR()
1748 SB.TmpVGPR) in spillSGPR()
1751 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillSGPR()
1763 if (SB.NumSubRegs > 1) { in spillSGPR()
1766 if (i + 1 == SB.NumSubRegs) in spillSGPR()
1767 SuperKillState |= getKillRegState(SB.IsKill); in spillSGPR()
1768 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState); in spillSGPR()
1773 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false); in spillSGPR()
1776 SB.restore(); in spillSGPR()
1780 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs); in spillSGPR()
1783 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in spillSGPR()
1793 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR() local
1795 ArrayRef<SpilledReg> VGPRSpills = SB.MFI.getSGPRToVGPRSpills(Index); in restoreSGPR()
1801 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in restoreSGPR()
1803 SB.NumSubRegs == 1 in restoreSGPR()
1804 ? SB.SuperReg in restoreSGPR()
1805 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in restoreSGPR()
1808 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), in restoreSGPR()
1812 if (SB.NumSubRegs > 1 && i == 0) in restoreSGPR()
1813 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1823 SB.prepare(); in restoreSGPR()
1826 auto PVD = SB.getPerVGPRData(); in restoreSGPR()
1830 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ true); in restoreSGPR()
1834 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in restoreSGPR()
1837 SB.NumSubRegs == 1 in restoreSGPR()
1838 ? SB.SuperReg in restoreSGPR()
1839 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in restoreSGPR()
1842 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in restoreSGPR()
1843 SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1844 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg)) in restoreSGPR()
1846 if (SB.NumSubRegs > 1 && i == 0) in restoreSGPR()
1847 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1857 SB.restore(); in restoreSGPR()
1863 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in restoreSGPR()
1871 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR() local
1873 SB.prepare(); in spillEmergencySGPR()
1875 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillEmergencySGPR()
1876 auto PVD = SB.getPerVGPRData(); in spillEmergencySGPR()
1881 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillEmergencySGPR()
1884 SB.NumSubRegs == 1 in spillEmergencySGPR()
1885 ? SB.SuperReg in spillEmergencySGPR()
1886 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillEmergencySGPR()
1889 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillEmergencySGPR()
1890 SB.TmpVGPR) in spillEmergencySGPR()
1893 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillEmergencySGPR()
1897 if (SB.NumSubRegs > 1) { in spillEmergencySGPR()
1900 if (i + 1 == SB.NumSubRegs) in spillEmergencySGPR()
1901 SuperKillState |= getKillRegState(SB.IsKill); in spillEmergencySGPR()
1902 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState); in spillEmergencySGPR()
1910 SB.setMI(&RestoreMBB, MI); in spillEmergencySGPR()
1916 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillEmergencySGPR()
1919 SB.NumSubRegs == 1 in spillEmergencySGPR()
1920 ? SB.SuperReg in spillEmergencySGPR()
1921 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillEmergencySGPR()
1923 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), in spillEmergencySGPR()
1925 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg)) in spillEmergencySGPR()
1927 if (SB.NumSubRegs > 1 && i == 0) in spillEmergencySGPR()
1928 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
1931 SB.restore(); in spillEmergencySGPR()
1933 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs); in spillEmergencySGPR()