381 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,  in reserveRegisterTuples()  argument
386     Reserved.set(*R);  in reserveRegisterTuples()
546   BitVector Reserved(getNumRegs());  in getReservedRegs()  local
547   Reserved.set(AMDGPU::MODE);  in getReservedRegs()
555   reserveRegisterTuples(Reserved, AMDGPU::EXEC);  in getReservedRegs()
556   reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);  in getReservedRegs()
559   reserveRegisterTuples(Reserved, AMDGPU::M0);  in getReservedRegs()
562   reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ);  in getReservedRegs()
563   reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ);  in getReservedRegs()
564   reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC);  in getReservedRegs()
567   reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);  in getReservedRegs()
568   reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);  in getReservedRegs()
569   reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);  in getReservedRegs()
570   reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);  in getReservedRegs()
573   reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID);  in getReservedRegs()
576   reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);  in getReservedRegs()
579   reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT);  in getReservedRegs()
582   reserveRegisterTuples(Reserved, AMDGPU::TBA);  in getReservedRegs()
583   reserveRegisterTuples(Reserved, AMDGPU::TMA);  in getReservedRegs()
584   reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);  in getReservedRegs()
585   reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);  in getReservedRegs()
586   reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);  in getReservedRegs()
587   reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);  in getReservedRegs()
588   reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);  in getReservedRegs()
589   reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);  in getReservedRegs()
590   reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);  in getReservedRegs()
591   reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);  in getReservedRegs()
594   reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL64);  in getReservedRegs()
599     Reserved.set(AMDGPU::VCC);  in getReservedRegs()
600     Reserved.set(AMDGPU::VCC_HI);  in getReservedRegs()
609     reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
613     Reserved.set(getSubReg(Reg, AMDGPU::hi16));  in getReservedRegs()
617       Reserved.set(Low);  in getReservedRegs()
625     reserveRegisterTuples(Reserved, ScratchRSrcReg);  in getReservedRegs()
633     reserveRegisterTuples(Reserved, StackPtrReg);  in getReservedRegs()
639     reserveRegisterTuples(Reserved, FrameReg);  in getReservedRegs()
645     reserveRegisterTuples(Reserved, BasePtrReg);  in getReservedRegs()
659       reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
664     Reserved.set(getSubReg(Reg, AMDGPU::hi16));  in getReservedRegs()
690     reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
695     reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
701     reserveRegisterTuples(Reserved, MFI->getVGPRForAGPRCopy());  in getReservedRegs()
705     reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
709     reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
712     reserveRegisterTuples(Reserved, Reg);  in getReservedRegs()
715     reserveRegisterTuples(Reserved, SSpill.VGPR);  in getReservedRegs()
717   return Reserved;  in getReservedRegs()