Lines Matching refs:IsKill
84 bool IsKill; member
120 bool IsKill, int Index, RegScavenger *RS) in SGPRSpillBuilder()
121 : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()), in SGPRSpillBuilder()
1155 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1179 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1187 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1272 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1494 SrcDstRegState |= getKillRegState(IsKill); in buildSpillLoadStore()
1519 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); in buildSpillLoadStore()
1562 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
1583 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
1638 bool IsKill) const { in buildVGPRSpillLoadStore()
1662 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill, in buildVGPRSpillLoadStore()
1696 bool UseKill = SB.IsKill && i == SB.NumSubRegs - 1; in spillSGPR()
1729 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillSGPR()
1767 SuperKillState |= getKillRegState(SB.IsKill); in spillSGPR()
1875 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillEmergencySGPR()
1901 SuperKillState |= getKillRegState(SB.IsKill); in spillEmergencySGPR()