Lines Matching refs:FIOp
875 MachineOperand *FIOp = in resolveFrameIndex() local
882 assert(FIOp && FIOp->isFI() && "frame index must be address operand"); in resolveFrameIndex()
889 FIOp->ChangeToRegister(BaseReg, false); in resolveFrameIndex()
902 FIOp->ChangeToRegister(BaseReg, false); in resolveFrameIndex()
1985 MachineOperand &FIOp = MI->getOperand(FIOperandNum); in eliminateFrameIndex() local
2129 FIOp.ChangeToRegister(FrameReg, false); in eliminateFrameIndex()
2166 FIOp.ChangeToImmediate(Offset); in eliminateFrameIndex()
2167 if (TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) in eliminateFrameIndex()
2173 FIOp.ChangeToRegister(AMDGPU::M0, false); in eliminateFrameIndex()
2174 bool UseSGPR = TII->isOperandLegal(*MI, FIOperandNum, &FIOp); in eliminateFrameIndex()
2177 FIOp.setReg(FrameReg); in eliminateFrameIndex()
2185 FIOp.setReg(TmpReg); in eliminateFrameIndex()
2186 FIOp.setIsKill(true); in eliminateFrameIndex()
2212 FIOp.setReg(FrameReg); in eliminateFrameIndex()
2213 FIOp.setIsKill(false); in eliminateFrameIndex()
2349 FIOp.ChangeToRegister(ResultReg, false, false, true); in eliminateFrameIndex()
2380 FIOp.ChangeToImmediate(Offset); in eliminateFrameIndex()
2381 if (!TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) { in eliminateFrameIndex()
2385 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()