358   Register ScratchRsrcReg = MFI->getScratchRSrcReg();  in getEntryFunctionReservedScratchRsrcReg()  local
360   if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) &&  in getEntryFunctionReservedScratchRsrcReg()
365       ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))  in getEntryFunctionReservedScratchRsrcReg()
366     return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
390       MRI.replaceRegWith(ScratchRsrcReg, Reg);  in getEntryFunctionReservedScratchRsrcReg()
396   return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
437   Register ScratchRsrcReg;  in emitEntryFunctionPrologue()  local
439     ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);  in emitEntryFunctionPrologue()
442   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
445         OtherBB.addLiveIn(ScratchRsrcReg);  in emitEntryFunctionPrologue()
456     if (ScratchRsrcReg && PreloadedScratchRsrcReg) {  in emitEntryFunctionPrologue()
476       TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {  in emitEntryFunctionPrologue()
484           !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {  in emitEntryFunctionPrologue()
514   if ((NeedsFlatScratchInit || ScratchRsrcReg) &&  in emitEntryFunctionPrologue()
524   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
527                                          ScratchRsrcReg, ScratchWaveOffsetReg);  in emitEntryFunctionPrologue()
535     Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const {  in emitEntryFunctionScratchRsrcRegSetup()  argument
546     Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
547     Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
563     BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
567       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)  in emitEntryFunctionScratchRsrcRegSetup()
587     Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);  in emitEntryFunctionScratchRsrcRegSetup()
588     Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
594       Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
601           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
616           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
622       Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
623       Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
627         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
631         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
637       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
641       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
645     if (ScratchRsrcReg != PreloadedScratchRsrcReg) {  in emitEntryFunctionScratchRsrcRegSetup()
646       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
660   Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
661   Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
668       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
672       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()