217   SDValue Lo = N->getOperand(0);  in matchLoadD16FromBuildVector()  local
228   if (LdHi && Hi.hasOneUse() && !LdHi->isPredecessorOf(Lo.getNode())) {  in matchLoadD16FromBuildVector()
231     SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);  in matchLoadD16FromBuildVector()
257   LoadSDNode *LdLo = dyn_cast<LoadSDNode>(stripBitcast(Lo));  in matchLoadD16FromBuildVector()
258   if (LdLo && Lo.hasOneUse()) {  in matchLoadD16FromBuildVector()
439   SDNode *Lo = CurDAG->getMachineNode(  in buildSMovImm64()  local
447       SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),  in buildSMovImm64()
744     SDValue Lo = Addr.getOperand(0).getOperand(0);  in getBaseWithOffsetUsingSplitOR()  local
745     if (Lo.getOpcode() == ISD::OR && DAG.isBaseWithConstantOffset(Lo)) {  in getBaseWithOffsetUsingSplitOR()
746       SDValue BaseLo = Lo.getOperand(0);  in getBaseWithOffsetUsingSplitOR()
759         N1 = Lo.getOperand(1);  in getBaseWithOffsetUsingSplitOR()
1041     SDNode *Lo = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SL,  in SelectMUL_LOHI()  local
1043     ReplaceUses(SDValue(N, 0), SDValue(Lo, 0));  in SelectMUL_LOHI()
2711     SDValue Lo = stripBitcast(Src.getOperand(0));  in SelectVOP3PMods()  local
2714     if (Lo.getOpcode() == ISD::FNEG) {  in SelectVOP3PMods()
2715       Lo = stripBitcast(Lo.getOperand(0));  in SelectVOP3PMods()
2724     if (isExtractHiElt(Lo, Lo))  in SelectVOP3PMods()
2731     Lo = stripExtractLoElt(Lo);  in SelectVOP3PMods()
2734     if (Lo.getValueSizeInBits() > VecSize) {  in SelectVOP3PMods()
2735       Lo = CurDAG->getTargetExtractSubreg(  in SelectVOP3PMods()
2737         MVT::getIntegerVT(VecSize), Lo);  in SelectVOP3PMods()
2746     assert(Lo.getValueSizeInBits() <= VecSize &&  in SelectVOP3PMods()
2749     if (Lo == Hi && !isInlineImmediate(Lo.getNode())) {  in SelectVOP3PMods()
2753       if (VecSize == 32 || VecSize == Lo.getValueSizeInBits()) {  in SelectVOP3PMods()
2754         Src = Lo;  in SelectVOP3PMods()
2756         assert(Lo.getValueSizeInBits() == 32 && VecSize == 64);  in SelectVOP3PMods()
2761                                  Lo.getValueType()), 0);  in SelectVOP3PMods()
2762         auto RC = Lo->isDivergent() ? AMDGPU::VReg_64RegClassID  in SelectVOP3PMods()
2766           Lo, CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32),  in SelectVOP3PMods()
2776     if (VecSize == 64 && Lo == Hi && isa<ConstantFPSDNode>(Lo)) {  in SelectVOP3PMods()
2777       uint64_t Lit = cast<ConstantFPSDNode>(Lo)->getValueAPF()  in SelectVOP3PMods()