Lines Matching refs:Op0
781 SDValue Op0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local
784 DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
787 return Op0; in SimplifyMultipleUseDemandedBits()
792 SDValue Op0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local
799 Op0.getScalarValueSizeInBits() == BitWidth && in SimplifyMultipleUseDemandedBits()
800 getBooleanContents(Op0.getValueType()) == in SimplifyMultipleUseDemandedBits()
808 return Op0; in SimplifyMultipleUseDemandedBits()
814 SDValue Op0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local
818 return Op0; in SimplifyMultipleUseDemandedBits()
820 unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); in SimplifyMultipleUseDemandedBits()
822 return Op0; in SimplifyMultipleUseDemandedBits()
1313 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1319 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO, in SimplifyDemandedBits()
1333 Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1337 Op0 = DemandedOp0 ? DemandedOp0 : Op0; in SimplifyDemandedBits()
1339 SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask); in SimplifyDemandedBits()
1346 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1355 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth); in SimplifyDemandedBits()
1359 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1372 if (isBitwiseNot(Op0) && Op0.hasOneUse() && in SimplifyDemandedBits()
1374 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1); in SimplifyDemandedBits()
1381 if (Op0.getOpcode() == ISD::INSERT_SUBVECTOR && in SimplifyDemandedBits()
1382 (Op0.getOperand(0).isUndef() || in SimplifyDemandedBits()
1383 ISD::isBuildVectorOfConstantSDNodes(Op0.getOperand(0).getNode())) && in SimplifyDemandedBits()
1384 Op0->hasOneUse()) { in SimplifyDemandedBits()
1386 Op0.getOperand(1).getValueType().getVectorNumElements(); in SimplifyDemandedBits()
1387 unsigned SubIdx = Op0.getConstantOperandVal(2); in SimplifyDemandedBits()
1394 TLO.DAG.getNode(ISD::AND, dl, VT, Op0.getOperand(0), Op1); in SimplifyDemandedBits()
1397 Op0.getOperand(1), Op0.getOperand(2)); in SimplifyDemandedBits()
1406 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts, in SimplifyDemandedBits()
1414 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1431 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1435 Op0 = DemandedOp0 ? DemandedOp0 : Op0; in SimplifyDemandedBits()
1437 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); in SimplifyDemandedBits()
1446 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1453 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, in SimplifyDemandedBits()
1461 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1474 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1478 Op0 = DemandedOp0 ? DemandedOp0 : Op0; in SimplifyDemandedBits()
1480 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); in SimplifyDemandedBits()
1487 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::AND && in SimplifyDemandedBits()
1488 Op0->hasOneUse() && Op1->hasOneUse()) { in SimplifyDemandedBits()
1516 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1523 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
1531 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1542 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
1554 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC)); in SimplifyDemandedBits()
1562 SDValue New = TLO.DAG.getNOT(dl, Op0, VT); in SimplifyDemandedBits()
1566 unsigned Op0Opcode = Op0.getOpcode(); in SimplifyDemandedBits()
1567 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { in SimplifyDemandedBits()
1569 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) { in SimplifyDemandedBits()
1584 SDValue Not = TLO.DAG.getNOT(dl, Op0.getOperand(0), VT); in SimplifyDemandedBits()
1586 Op0.getOperand(1))); in SimplifyDemandedBits()
1601 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1605 Op0 = DemandedOp0 ? DemandedOp0 : Op0; in SimplifyDemandedBits()
1607 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1); in SimplifyDemandedBits()
1663 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1670 Op0.getScalarValueSizeInBits() == BitWidth && in SimplifyDemandedBits()
1671 getBooleanContents(Op0.getValueType()) == in SimplifyDemandedBits()
1679 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1684 if (getBooleanContents(Op0.getValueType()) == in SimplifyDemandedBits()
1691 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1699 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1705 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1708 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { in SimplifyDemandedBits()
1718 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); in SimplifyDemandedBits()
1726 if (Op0.getOpcode() == ISD::ANY_EXTEND) { in SimplifyDemandedBits()
1727 SDValue InnerOp = Op0.getOperand(0); in SimplifyDemandedBits()
1748 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
1769 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1781 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1799 if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1821 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
1824 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1829 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1842 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1848 if (Op0.getOpcode() == ISD::SHL) { in SimplifyDemandedBits()
1851 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) { in SimplifyDemandedBits()
1861 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); in SimplifyDemandedBits()
1874 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1886 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1893 if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >= in SimplifyDemandedBits()
1895 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1902 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
1913 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
1927 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
1941 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
1948 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
1958 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
1969 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
1980 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts, in SimplifyDemandedBits()
1990 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2008 Op0, Demanded0, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2012 DemandedOp0 = DemandedOp0 ? DemandedOp0 : Op0; in SimplifyDemandedBits()
2032 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
2037 if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1)) in SimplifyDemandedBits()
2038 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
2047 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2053 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
2059 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
2064 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
2079 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
2081 KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
2085 return TLO.CombineTo(Op, IsULE.value() ? Op0 : Op1); in SimplifyDemandedBits()
2087 return TLO.CombineTo(Op, IsULT.value() ? Op0 : Op1); in SimplifyDemandedBits()
2092 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
2094 KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
2098 return TLO.CombineTo(Op, IsUGE.value() ? Op0 : Op1); in SimplifyDemandedBits()
2100 return TLO.CombineTo(Op, IsUGT.value() ? Op0 : Op1); in SimplifyDemandedBits()
2160 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedBits() local
2167 TLO.DAG.ComputeMaxSignificantBits(Op0, DemandedElts, Depth + 1); in SimplifyDemandedBits()
2177 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt)); in SimplifyDemandedBits()
2183 return TLO.CombineTo(Op, Op0); in SimplifyDemandedBits()
2191 if (SimplifyDemandedBits(Op0, InputDemandedBits, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2201 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT)); in SimplifyDemandedBits()
2584 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); in SimplifyDemandedBits() local
2588 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO, in SimplifyDemandedBits()
2607 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
2613 Op0 = DemandedOp0 ? DemandedOp0 : Op0; in SimplifyDemandedBits()
2616 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); in SimplifyDemandedBits()
2635 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); in SimplifyDemandedBits()
2669 if (unsigned ShAmt = getShiftLeftAmt(Op0)) in SimplifyDemandedBits()
2670 return foldMul(ISD::SUB, Op0.getOperand(0), Op1, ShAmt); in SimplifyDemandedBits()
2673 return foldMul(ISD::SUB, Op1.getOperand(0), Op0, ShAmt); in SimplifyDemandedBits()
2678 return foldMul(ISD::ADD, Op1.getOperand(0), Op0, ShAmt); in SimplifyDemandedBits()
2836 auto SimplifyDemandedVectorEltsBinOp = [&](SDValue Op0, SDValue Op1) { in SimplifyDemandedVectorElts() argument
2837 SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts, in SimplifyDemandedVectorElts()
2843 Opcode, SDLoc(Op), VT, NewOp0 ? NewOp0 : Op0, NewOp1 ? NewOp1 : Op1); in SimplifyDemandedVectorElts()
3302 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3304 if (Op0 == Op1 && Op->isOnlyUserOf(Op0.getNode())) { in SimplifyDemandedVectorElts()
3306 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, in SimplifyDemandedVectorElts()
3320 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3328 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, in SimplifyDemandedVectorElts()
3338 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) in SimplifyDemandedVectorElts()
3347 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3355 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO, in SimplifyDemandedVectorElts()
3365 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) in SimplifyDemandedVectorElts()
3371 SDValue Op0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3378 if (SimplifyDemandedVectorElts(Op0, DemandedElts, KnownUndef, KnownZero, in SimplifyDemandedVectorElts()
3398 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) in SimplifyDemandedVectorElts()
4484 SDValue Op0 = N0; in SimplifySetCC() local
4485 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
4486 Op0 = Op0.getOperand(0); in SimplifySetCC()
4488 if ((Op0.getOpcode() == ISD::XOR) && in SimplifySetCC()
4489 Op0.getOperand(0).getOpcode() == ISD::SETCC && in SimplifySetCC()
4490 Op0.getOperand(1).getOpcode() == ISD::SETCC) { in SimplifySetCC()
4491 SDValue XorLHS = Op0.getOperand(0); in SimplifySetCC()
4492 SDValue XorRHS = Op0.getOperand(1); in SimplifySetCC()
4494 if (Op0.getValueType() == MVT::i1 || in SimplifySetCC()
4504 if (Op0.getOpcode() == ISD::AND && isOneConstant(Op0.getOperand(1))) { in SimplifySetCC()
4506 if (Op0.getValueType().bitsGT(VT)) in SimplifySetCC()
4507 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
4508 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
4510 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
4511 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
4512 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
4515 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
4516 DAG.getConstant(0, dl, Op0.getValueType()), in SimplifySetCC()
4519 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
4520 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
4521 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
4522 DAG.getConstant(0, dl, Op0.getValueType()), in SimplifySetCC()
5682 SDValue Op0 = N->getOperand(0); in BuildExactSDIV() local
5731 SDValue Res = Op0; in BuildExactSDIV()
6296 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); in prepareUREMEqFold() local
6297 Created.push_back(Op0.getNode()); in prepareUREMEqFold()
6306 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); in prepareUREMEqFold()
6307 Created.push_back(Op0.getNode()); in prepareUREMEqFold()
6312 DAG.getSetCC(DL, SETCCVT, Op0, QVal, in prepareUREMEqFold()
6551 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); in prepareSREMEqFold() local
6552 Created.push_back(Op0.getNode()); in prepareSREMEqFold()
6560 Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal); in prepareSREMEqFold()
6561 Created.push_back(Op0.getNode()); in prepareSREMEqFold()
6571 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); in prepareSREMEqFold()
6572 Created.push_back(Op0.getNode()); in prepareSREMEqFold()
6577 DAG.getSetCC(DL, SETCCVT, Op0, QVal, in prepareSREMEqFold()
7224 SDValue Op0 = Node->getOperand(0); in expandROT() local
7236 return DAG.getNode(RevRot, DL, VT, Op0, Sub); in expandROT()
7257 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
7259 HsVal = DAG.getNode(HsOpc, DL, VT, Op0, HsAmt); in expandROT()
7265 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
7269 DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt); in expandROT()
8821 SDValue Op0 = Node->getOperand(0); in expandIntMINMAX() local
8823 EVT VT = Op0.getValueType(); in expandIntMINMAX()
8830 return DAG.getNode(ISD::SUB, DL, VT, Op0, in expandIntMINMAX()
8831 DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); in expandIntMINMAX()
8837 return DAG.getNode(ISD::ADD, DL, VT, Op0, in expandIntMINMAX()
8838 DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); in expandIntMINMAX()
8857 SDValue Cond = DAG.getSetCC(DL, BoolVT, Op0, Op1, CC); in expandIntMINMAX()
8858 return DAG.getSelect(DL, VT, Cond, Op0, Op1); in expandIntMINMAX()