Lines Matching refs:DCI
598 DAGCombinerInfo &DCI) const { in SimplifyDemandedBits()
599 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits()
600 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
601 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
606 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedBits()
607 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedBits()
614 DAGCombinerInfo &DCI) const { in SimplifyDemandedBits()
615 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedBits()
616 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
617 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
623 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedBits()
624 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedBits()
2723 DAGCombinerInfo &DCI) const { in SimplifyDemandedVectorElts()
2724 SelectionDAG &DAG = DCI.DAG; in SimplifyDemandedVectorElts()
2725 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
2726 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
2732 DCI.AddToWorklist(Op.getNode()); in SimplifyDemandedVectorElts()
2733 DCI.CommitTargetLoweringOpt(TLO); in SimplifyDemandedVectorElts()
3674 DAGCombinerInfo &DCI) const { in foldSetCCWithAnd()
3678 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithAnd()
3717 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
3753 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, in optimizeSetCCOfSignedTruncationCheck() argument
3822 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCOfSignedTruncationCheck()
3843 DAGCombinerInfo &DCI, const SDLoc &DL) const { in optimizeSetCCByHoistingAndByConstFromLogicalShift() argument
3853 SelectionDAG &DAG = DCI.DAG; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
3916 DAGCombinerInfo &DCI) const { in foldSetCCWithBinOp()
3925 SelectionDAG &DAG = DCI.DAG; in foldSetCCWithBinOp()
3946 !DCI.isBeforeLegalize()); in foldSetCCWithBinOp()
3949 if (!DCI.isCalledByLegalizer()) in foldSetCCWithBinOp()
3950 DCI.AddToWorklist(YShl1.getNode()); in foldSetCCWithBinOp()
4135 DAGCombinerInfo &DCI, in SimplifySetCC() argument
4137 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
4156 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4165 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4217 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4304 if (DCI.isBeforeLegalize() && in SimplifySetCC()
4398 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4432 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
4433 DCI.AddToWorklist(ZextOp.getNode()); in SimplifySetCC()
4451 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4551 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
4580 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4600 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4616 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4634 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4651 VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
4719 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4756 getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
4782 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC()
4843 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4889 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4957 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI)) in SimplifySetCC()
4963 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI)) in SimplifySetCC()
4966 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI)) in SimplifySetCC()
4979 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
4982 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
4996 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
4997 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5006 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5007 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5013 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5014 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5020 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5021 DCI.AddToWorklist(Temp.getNode()); in SimplifySetCC()
5030 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
5031 DCI.AddToWorklist(N0.getNode()); in SimplifySetCC()
5076 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
6117 DAGCombinerInfo &DCI, in buildUREMEqFold() argument
6121 DCI, DL, Built)) { in buildUREMEqFold()
6123 DCI.AddToWorklist(N); in buildUREMEqFold()
6133 DAGCombinerInfo &DCI, const SDLoc &DL, in prepareUREMEqFold() argument
6143 SelectionDAG &DAG = DCI.DAG; in prepareUREMEqFold()
6147 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareUREMEqFold()
6151 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
6288 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
6303 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6360 DAGCombinerInfo &DCI, in buildSREMEqFold() argument
6364 DCI, DL, Built)) { in buildSREMEqFold()
6367 DCI.AddToWorklist(N); in buildSREMEqFold()
6377 DAGCombinerInfo &DCI, const SDLoc &DL, in prepareSREMEqFold() argument
6392 SelectionDAG &DAG = DCI.DAG; in prepareSREMEqFold()
6396 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout(), !DCI.isBeforeLegalize()); in prepareSREMEqFold()
6401 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
6556 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
6568 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()