1436     LiveInterval &DstInt = LIS->getInterval(DstReg);  in reMaterializeTrivialDef()  local
1437     for (LiveInterval::SubRange &SR : DstInt.subranges()) {  in reMaterializeTrivialDef()
1464     if (NewIdx == 0 && DstInt.hasSubRanges()) {  in reMaterializeTrivialDef()
1470       for (LiveInterval::SubRange &SR : DstInt.subranges()) {  in reMaterializeTrivialDef()
1476         LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask);  in reMaterializeTrivialDef()
1489     if (NewIdx != 0 && DstInt.hasSubRanges()) {  in reMaterializeTrivialDef()
1497       for (LiveInterval::SubRange &SR : DstInt.subranges()) {  in reMaterializeTrivialDef()
1518         DstInt.removeEmptySubRanges();  in reMaterializeTrivialDef()
1748   LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);  in updateRegDefsUses()  local
1750   if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {  in updateRegDefsUses()
1759       addUndefFlag(*DstInt, UseIdx, MO, SubReg);  in updateRegDefsUses()
1783     if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr())  in updateRegDefsUses()
1784       Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));  in updateRegDefsUses()
1801           if (!DstInt->hasSubRanges()) {  in updateRegDefsUses()
1803             LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(DstInt->reg());  in updateRegDefsUses()
1806             DstInt->createSubRangeFrom(Allocator, UsedLanes, *DstInt);  in updateRegDefsUses()
1811             DstInt->createSubRange(Allocator, UnusedLanes);  in updateRegDefsUses()
1817           addUndefFlag(*DstInt, UseIdx, MO, SubUseIdx);  in updateRegDefsUses()