98       bool LiveOut = false;            ///< Register is possibly live out.  member
286                MCPhysReg AssignedReg, bool Kill, bool LiveOut);
424                          MCPhysReg AssignedReg, bool Kill, bool LiveOut) {  in spill()  argument
455     if (LiveOut) {  in spill()
653                        findLiveVirtReg(VirtReg)->LiveOut;  in calcSpillCost()
910         LRI->LiveOut = true;  in defineVirtReg()
929   if (LRI->Reloaded || LRI->LiveOut) {  in defineVirtReg()
933       LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut << " RL: "  in defineVirtReg()
936       spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);  in defineVirtReg()
939     LRI->LiveOut = false;  in defineVirtReg()
961         LRI->LiveOut = true;  in useVirtReg()
1052       if (I->LiveOut || I->Reloaded) {  in dumpState()
1054         if (I->LiveOut) dbgs() << 'O';  in dumpState()