Lines Matching refs:self
14 def test_x86_64_regs(self): argument
46 def qXferRead(self, obj, annex, offset, length): argument
114 def readRegister(self, regnum): argument
117 def readRegisters(self): argument
118 return self.reg_data
120 def writeRegisters(self, reg_hex): argument
121 self.reg_data = reg_hex
124 def haltReason(self): argument
127 self.server.responder = MyResponder()
129 target = self.createTarget("basic_eh_frame.yaml")
130 process = self.connect(target)
131 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
135 self.match("register read arg4",
137 self.match("register read arg3",
139 self.match("register read arg2",
141 self.match("register read arg1",
143 self.match("register read fp",
145 self.match("register read sp",
147 self.match("register read arg5",
149 self.match("register read arg6",
151 self.match("register read pc",
153 self.match("register read flags",
157 self.match("register read st0",
159 self.match("register read st1",
161 self.match("register read xmm0",
164 self.match("register read xmm1",
169 self.filecheck("register read --all",
174 self.runCmd("register write ecx 0xfffefdfc")
175 self.match("register read rcx",
178 self.runCmd("register write cx 0xfbfa")
179 self.match("register read ecx",
181 self.match("register read rcx",
184 self.runCmd("register write ch 0xf9")
185 self.match("register read cx",
187 self.match("register read ecx",
189 self.match("register read rcx",
192 self.runCmd("register write cl 0xf8")
193 self.match("register read cx",
195 self.match("register read ecx",
197 self.match("register read rcx",
200 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8")
201 self.match("register read st0",
204 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
206 self.match("register read ymm0",
211 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
213 self.match("register read ymm0",
218 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
222 self.match("register read ymm0",
230 def test_i386_regs(self): argument
262 def qXferRead(self, obj, annex, offset, length): argument
314 def readRegister(self, regnum): argument
317 def readRegisters(self): argument
318 return self.reg_data
320 def writeRegisters(self, reg_hex): argument
321 self.reg_data = reg_hex
324 def haltReason(self): argument
327 self.server.responder = MyResponder()
329 target = self.createTarget("basic_eh_frame-i386.yaml")
330 process = self.connect(target)
331 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
335 self.match("register read fp",
337 self.match("register read sp",
339 self.match("register read pc",
341 self.match("register read flags",
345 self.match("register read cx",
347 self.match("register read ch",
349 self.match("register read cl",
351 self.match("register read mm0",
353 self.match("register read mm1",
357 self.match("register read st0",
359 self.match("register read st1",
361 self.match("register read xmm0",
364 self.match("register read xmm1",
369 self.runCmd("register write cx 0xfbfa")
370 self.match("register read ecx",
373 self.runCmd("register write ch 0xf9")
374 self.match("register read cx",
376 self.match("register read ecx",
379 self.runCmd("register write cl 0xf8")
380 self.match("register read cx",
382 self.match("register read ecx",
385 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8")
386 self.match("register read st0",
389 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
391 self.match("register read ymm0",
396 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
398 self.match("register read ymm0",
403 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
407 self.match("register read ymm0",
415 def test_aarch64_regs(self): argument
438 def qXferRead(self, obj, annex, offset, length): argument
520 def readRegister(self, regnum): argument
523 def readRegisters(self): argument
524 return self.reg_data
526 def writeRegisters(self, reg_hex): argument
527 self.reg_data = reg_hex
530 def haltReason(self): argument
533 self.server.responder = MyResponder()
535 target = self.createTarget("basic_eh_frame-aarch64.yaml")
536 process = self.connect(target)
537 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
541 self.match("register read x0",
543 self.match("register read x1",
545 self.match("register read x29",
547 self.match("register read x30",
549 self.match("register read x31",
551 self.match("register read sp",
553 self.match("register read pc",
555 self.match("register read cpsr",
559 self.match("register read arg1",
561 self.match("register read arg2",
563 self.match("register read fp",
565 self.match("register read lr",
567 self.match("register read ra",
569 self.match("register read flags",
573 self.match("register read v0",
575 self.match("register read v31",
579 self.match("register read w0",
581 self.runCmd("register write w0 0xfffefdfc")
582 self.match("register read x0",
585 self.match("register read w1",
587 self.runCmd("register write w1 0xefeeedec")
588 self.match("register read x1",
591 self.match("register read w30",
593 self.runCmd("register write w30 0xdfdedddc")
594 self.match("register read x30",
597 self.match("register read w31",
599 self.runCmd("register write w31 0xcfcecdcc")
600 self.match("register read x31",
604 self.runCmd("register write d0 16")
605 self.match("register read v0",
607 …self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff…
608 self.match("register read d31",
611 self.runCmd("register write s0 32")
612 self.match("register read v0",
614 …self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
615 self.match("register read s31",
621 def test_x86_64_no_duplicate_subregs(self): argument
637 def qXferRead(self, obj, annex, offset, length): argument
661 def readRegister(self, regnum): argument
664 def readRegisters(self): argument
665 return self.reg_data
667 def haltReason(self): argument
670 self.server.responder = MyResponder()
672 target = self.createTarget("basic_eh_frame.yaml")
673 process = self.connect(target)
674 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
677 self.match("register read rcx",
680 self.match("register read ecx",
682 self.match("register read rdx",
685 self.match("register read edx",
692 def test_i386_no_duplicate_subregs(self): argument
708 def qXferRead(self, obj, annex, offset, length): argument
732 def readRegister(self, regnum): argument
735 def readRegisters(self): argument
736 return self.reg_data
738 def haltReason(self): argument
741 self.server.responder = MyResponder()
743 target = self.createTarget("basic_eh_frame-i386.yaml")
744 process = self.connect(target)
745 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
748 self.match("register read eax",
751 self.match("register read ax",
753 self.match("register read ecx",
756 self.match("register read cx",
763 def test_aarch64_no_duplicate_subregs(self): argument
779 def qXferRead(self, obj, annex, offset, length): argument
826 def readRegister(self, regnum): argument
829 def readRegisters(self): argument
830 return self.reg_data
832 def haltReason(self): argument
835 self.server.responder = MyResponder()
837 target = self.createTarget("basic_eh_frame-aarch64.yaml")
838 process = self.connect(target)
839 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
842 self.match("register read x0",
845 self.match("register read w0",
847 self.match("register read x1",
850 self.match("register read w1",