Lines Matching refs:phases

327 // affect the phase, starting with the earliest phases, and record which
329 phases::ID Driver::getFinalPhase(const DerivedArgList &DAL,
332   phases::ID FinalPhase;
340     FinalPhase = phases::Preprocess;
349     FinalPhase = phases::Precompile;
360     FinalPhase = phases::Compile;
364     FinalPhase = phases::Backend;
368     FinalPhase = phases::Assemble;
371     FinalPhase = phases::IfsMerge;
375     FinalPhase = phases::Link;
2648     typedef const llvm::SmallVectorImpl<phases::ID> PhasesTy;
2690                          phases::ID CurPhase, phases::ID FinalPhase,
3060                          phases::ID CurPhase, phases::ID FinalPhase,
3081       if (CompileDeviceOnly || CurPhase == phases::Backend) {
3087             // Skip the phases that were already dealt with.
3097             if (Ph == phases::Assemble)
3143       } else if (CurPhase > phases::Backend) {
3150       assert(CurPhase < phases::Backend && "Generating single CUDA "
3210                          phases::ID CurPhase, phases::ID FinalPhase,
3216       // backend and assemble phases to output LLVM IR. Except for generating
3222       assert(((CurPhase == phases::Link && Relocatable) ||
3228       if (!Relocatable && CurPhase == phases::Backend && !EmitLLVM &&
3237             // When LTO is enabled, skip the backend and assemble phases and
3247             // compiler phases, including backend and assemble phases.
3260                   C, Args, phases::Backend, CudaDeviceActions[I],
3263                 C, Args, phases::Assemble, BackendAction,
3304       } else if (CurPhase == phases::Link) {
3420                          phases::ID CurPhase, phases::ID FinalPhase,
3431       if (CurPhase == phases::Link) {
3647                                    phases::ID CurPhase, phases::ID FinalPhase,
3904   phases::ID FinalPhase = getFinalPhase(Args, &FinalPhaseArg);
3906   if (FinalPhase == phases::Link) {
3916   if (FinalPhase == phases::Preprocess || Args.hasArg(options::OPT__SLASH_Y_)) {
3936     phases::ID InitialPhase = PL[0];
3955       else if (InitialPhase == phases::Compile &&
3974       if (FinalPhase >= phases::Compile) {
3978         for (phases::ID Phase : types::getCompilationPhases(HeaderType))
3994   if (FinalPhase == phases::Link && LastPLSize == 1) {
4084     for (phases::ID Phase : PL) {
4094       if (Phase == phases::Link) {
4108       if (Phase == phases::IfsMerge) {
4118       if (Phase == phases::Precompile && HeaderModuleAction &&
4125       if (Phase == phases::Precompile && ExtractAPIAction) {
4179     if (getFinalPhase(Args, &FinalPhaseArg) == phases::Link)
4213         Args.hasArg(options::OPT_c) ? phases::Compile : phases::IfsMerge);
4235         case phases::Compile: {
4245         case phases::IfsMerge: {
4412         getFinalPhase(Args) == phases::Preprocess))
4454     for (phases::ID Phase : PL) {
4455       if (Phase == phases::Link) {
4541     Compilation &C, const ArgList &Args, phases::ID Phase, Action *Input,
4548   if (Phase == phases::Assemble && Input->getType() != types::TY_PP_Asm)
4553   case phases::Link:
4555   case phases::IfsMerge:
4557   case phases::Preprocess: {
4581   case phases::Precompile: {
4610   case phases::Compile: {
4632   case phases::Backend: {
4654   case phases::Assemble: