Lines Matching refs:__uart_setreg
129 #define __uart_setreg(bas, reg, value) \ macro
176 __uart_setreg(bas, AUX_MU_CNTL_REG, line); in uart_mu_param()
190 __uart_setreg(bas, AUX_MU_LCR_REG, line); in uart_mu_param()
198 __uart_setreg(bas, AUX_MU_BAUD_REG, ((uint32_t)(baud & 0xFFFF))); in uart_mu_param()
202 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB); in uart_mu_param()
211 __uart_setreg(bas, AUX_MU_IER_REG, 0); in uart_mu_init()
227 __uart_setreg(bas, AUX_MU_IO_REG, c & 0xff); in uart_mu_putc()
314 __uart_setreg(bas, AUX_MU_IIR_REG, IIR_CLEAR); in uart_mu_bus_attach()
317 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier); in uart_mu_bus_attach()
393 __uart_setreg(bas, AUX_MU_IER_REG, in uart_mu_bus_ipend()
472 __uart_setreg(bas, AUX_MU_IO_REG, sc->sc_txbuf[i] & 0xff); in uart_mu_bus_transmit()
478 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier); in uart_mu_bus_transmit()
496 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier &~IER_MASK_ALL); in uart_mu_bus_grab()
511 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB); in uart_mu_bus_ungrab()
512 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier); in uart_mu_bus_ungrab()