1295 	struct puc_bar *bar;  in puc_config_advantech()  local
1350 		bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid);  in puc_config_advantech()
1351 		if (bar == NULL) {  in puc_config_advantech()
1367 		bus_write_1(bar->b_res, REG_SPR, REG_ACR);  in puc_config_advantech()
1368 		bus_write_1(bar->b_res, REG_ICR, acr);  in puc_config_advantech()
1468 	struct puc_bar *bar;  in puc_config_quatech()  local
1477 		bar = puc_get_bar(sc, cfg->rid);  in puc_config_quatech()
1478 		if (bar == NULL)  in puc_config_quatech()
1480 		bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);  in puc_config_quatech()
1481 		bus_write_1(bar->b_res, REG_SPR, 0);  in puc_config_quatech()
1482 		v0 = bus_read_1(bar->b_res, REG_SPR);  in puc_config_quatech()
1483 		bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);  in puc_config_quatech()
1484 		v1 = bus_read_1(bar->b_res, REG_SPR);  in puc_config_quatech()
1485 		bus_write_1(bar->b_res, REG_LCR, 0);  in puc_config_quatech()
1561 	struct puc_bar *bar;  in puc_config_syba()  local
1567 		bar = puc_get_bar(sc, cfg->rid);  in puc_config_syba()
1568 		if (bar == NULL)  in puc_config_syba()
1572 		bus_write_1(bar->b_res, 0x250, 0x89);  in puc_config_syba()
1573 		bus_write_1(bar->b_res, 0x3f0, 0x87);  in puc_config_syba()
1574 		bus_write_1(bar->b_res, 0x3f0, 0x87);  in puc_config_syba()
1578 			bus_write_1(bar->b_res, efir, 0x09);  in puc_config_syba()
1579 			v = bus_read_1(bar->b_res, efir + 1);  in puc_config_syba()
1582 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
1583 			v = bus_read_1(bar->b_res, efir + 1);  in puc_config_syba()
1584 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
1585 			bus_write_1(bar->b_res, efir + 1, v | 0x04);  in puc_config_syba()
1586 			bus_write_1(bar->b_res, efir, 0x16);  in puc_config_syba()
1587 			bus_write_1(bar->b_res, efir + 1, v & ~0x04);  in puc_config_syba()
1589 			bus_write_1(bar->b_res, efir, 0x23);  in puc_config_syba()
1590 			bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);  in puc_config_syba()
1591 			bus_write_1(bar->b_res, efir, 0x24);  in puc_config_syba()
1592 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);  in puc_config_syba()
1593 			bus_write_1(bar->b_res, efir, 0x25);  in puc_config_syba()
1594 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);  in puc_config_syba()
1595 			bus_write_1(bar->b_res, efir, 0x17);  in puc_config_syba()
1596 			bus_write_1(bar->b_res, efir + 1, 0x03);  in puc_config_syba()
1597 			bus_write_1(bar->b_res, efir, 0x28);  in puc_config_syba()
1598 			bus_write_1(bar->b_res, efir + 1, 0x43);  in puc_config_syba()
1601 		bus_write_1(bar->b_res, 0x250, 0xaa);  in puc_config_syba()
1602 		bus_write_1(bar->b_res, 0x3f0, 0xaa);  in puc_config_syba()
1766 	struct puc_bar *bar;  in puc_config_oxford_pcie()  local
1775 		bar = puc_get_bar(sc, cfg->rid);  in puc_config_oxford_pcie()
1776 		if (bar == NULL)  in puc_config_oxford_pcie()
1779 			value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +  in puc_config_oxford_pcie()
1781 			bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,  in puc_config_oxford_pcie()
1810 		bar = puc_get_bar(sc, cfg->rid);  in puc_config_oxford_pcie()
1811 		if (bar == NULL)  in puc_config_oxford_pcie()
1814 		value = bus_read_1(bar->b_res, 0x04);  in puc_config_oxford_pcie()