puc: Add support for Exar XR17V354 Quad PCI Express UART.

PR: 257207
MFC after: 1 week

(cherry picked from commit 5704277ae58b3498fbee2d041cd18d2444f5cf98)

sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of BSD-2-Clause.

Discussed with: pfg
MFC After: 3 days
Sponsored by: Netflix

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puc: clean up empty lines in .c and .h files

Miscellaneous typo fixes

Submitted by: Gordon Bergling <gbergling_gmail.com>
Differential Revision: https://reviews.freebsd.org/D23453

puc(4): Add provisional support for Exar XR17V352

Reportedly, this is sufficient for 4800bps use, but maybe not any better.

PR: 228781
Submitted by: peo AT nethead.se

sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error

sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

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- Add support for Advantech PCI-1602 Rev. B1 and PCI-1603 cards. [1]
- Add a description of Advantech PCI-1602 Rev. A boards. [1]
- Properly set up REG_ACR also for PCI-1602 Rev. A based on what the

- Add support for Advantech PCI-1602 Rev. B1 and PCI-1603 cards. [1]
- Add a description of Advantech PCI-1602 Rev. A boards. [1]
- Properly set up REG_ACR also for PCI-1602 Rev. A based on what the
Advantech-supplied Linux driver does.
- Additionally use the macros of <dev/ic/ns16550.h> to replace existing
magic values and get rid of trivial comments.
- Fix the style of some comments.

PR: 205359 [1]
Submitted by: Jan Mikkelsen (original patch) [1]

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- Add entries for the more prominent members of the Digi International
Neo series, which are based on Exar PCI chips.
- Mark some unused parameters as such.
- Fix style

MFC after: 3 days

- Add an entry for the SIIG Cyber 2SP1 PCIe adapter, which is based
on an Oxford Semiconductor OX16PCI954 but uses only two ports and
a non-default clock rate.
- Fix style/whitespace

PR: 176407

- Add an entry for the SIIG Cyber 2SP1 PCIe adapter, which is based
on an Oxford Semiconductor OX16PCI954 but uses only two ports and
a non-default clock rate.
- Fix style/whitespace

PR: 176407
MFC after: 3 days

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puc(4): Add an entry for the Feasso PCI FPP-02 2S1P card.

MFC after: 1 week

puc(4): add an entry for the Oxford Semiconductor OXPCIe952 1S1P card.

Submitted by: Alex Burlyga <alex.burlyga.ietf at gmail.com>
MFC after: 1 week

Correct a typo in a device description added in r264257.

Refine r264257; given that I later on decided to nuke the wildcard for
the Sunix 0x1999 line of chips there actually is no need to explicitly
keep puc(4) from attaching to the single port version any

Refine r264257; given that I later on decided to nuke the wildcard for
the Sunix 0x1999 line of chips there actually is no need to explicitly
keep puc(4) from attaching to the single port version anymore.

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Distinguish between the different variants and configurations of Sunix
{MIO,SER}5xxxx chips instead of treating all of them as PUC_PORT_2S.
Among others, this fixes the hang seen when trying to probe

Distinguish between the different variants and configurations of Sunix
{MIO,SER}5xxxx chips instead of treating all of them as PUC_PORT_2S.
Among others, this fixes the hang seen when trying to probe the none-
existent second UART on an actually 1-port chip.

Obtained from: NetBSD (BAR layouts)
MFC after: 3 days
Sponsored by: Bally Wulff Games & Entertainment GmbH

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Add MSI support to puc(9)

Add support for MSI interrupts in the puc(9) driver. By default the driver
will prefer MSI interrupts to legacy interrupts. A tunable,
hw.puc.msi_disable, has been added

Add MSI support to puc(9)

Add support for MSI interrupts in the puc(9) driver. By default the driver
will prefer MSI interrupts to legacy interrupts. A tunable,
hw.puc.msi_disable, has been added to force the allocation of legacy
interrupts.

Reviewed by: jhb@
MFC after: 2 weeks
Sponsored by: Sandvine Inc.

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All of Oxford/PLX OX16PCI954, OXm16PCI954 and OXu16PCI954 share the
exact same (subsystem) device and vendor IDs. However, the reference
design for the OXu16PCI954 uses a 14.7456 MHz clock (as does t

All of Oxford/PLX OX16PCI954, OXm16PCI954 and OXu16PCI954 share the
exact same (subsystem) device and vendor IDs. However, the reference
design for the OXu16PCI954 uses a 14.7456 MHz clock (as does the EXSYS
EX-41098-2 equipped with these), while at least the OX16PCI954 defaults
to a 1.8432 MHz one. According to the datasheets of these chips, the
only difference in PCI configuration space is that OXu16PCI954 have
a revision ID of 1 while the other two are at 0. So employ the latter
for determining the default clock rates of this family.
Note that one might think that the actual clock could be derived from
the Clock Prescaler Register (CPR) of these chips. Unfortunately, this
is not that case and its use and content are orthogonal to the frequency
of the crystal employed.
Tested with an EXSYS EX-41098-2, which identifies and attaches as:
pcib4@pci0:19:0:0: class=0x060400 card=0x02dd1014 chip=0x10801b21
rev=0x03 hdr=0x01
vendor = 'ASMedia Technology Inc.'
device = 'ASM1083/1085 PCIe to PCI Bridge'
class = bridge
subclass = PCI-PCI
puc0@pci0:20:4:0: class=0x070006 card=0x00001415 chip=0x95011415
rev=0x01 hdr=0x00
vendor = 'Oxford Semiconductor Ltd'
device = 'OX16PCI954 (Quad 16950 UART) function 0 (Uart)'
class = simple comms
subclass = UART
puc1@pci0:20:4:1: class=0x068000 card=0x00001415 chip=0x95111415
rev=0x01 hdr=0x00
vendor = 'Oxford Semiconductor Ltd'
device = 'OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)'
class = bridge
puc2@pci0:20:8:0: class=0x070006 card=0x00001415 chip=0x95011415
rev=0x01 hdr=0x00
vendor = 'Oxford Semiconductor Ltd'
device = 'OX16PCI954 (Quad 16950 UART) function 0 (Uart)'
class = simple comms
subclass = UART
puc3@pci0:20:8:1: class=0x068000 card=0x00001415 chip=0x95111415
rev=0x01 hdr=0x00
vendor = 'Oxford Semiconductor Ltd'
device = 'OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)'
class = bridge

pci20: <ACPI PCI bus> on pcib4
puc0: <Oxford Semiconductor OX16PCI954 UARTs> port 0x5000-0x501f,
0x5020-0x503f mem 0xc6000000-0xc6000fff,0xc6001000-0xc6001fff irq 16 at
device 4.0 on pci20
uart1: <16950 or compatible> at port 1 on puc0
uart2: <16950 or compatible> at port 2 on puc0
uart3: <16950 or compatible> at port 3 on puc0
uart4: <16950 or compatible> at port 4 on puc0
puc1: <Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)> port
0x5040-0x505f,0x5060-0x507f mem 0xc6002000-0xc6002fff,0xc6003000-0xc6003fff
irq 16 at device 4.1 on pci20
puc2: <Oxford Semiconductor OX16PCI954 UARTs> port 0x5080-0x509f,
0x50a0-0x50bf mem 0xc6004000-0xc6004fff,0xc6005000-0xc6005fff irq 16 at
device 8.0 on pci20
uart5: <16950 or compatible> at port 1 on puc2
uart6: <16950 or compatible> at port 2 on puc2
uart7: <16950 or compatible> at port 3 on puc2
uart8: <16950 or compatible> at port 4 on puc2
puc3: <Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)> port
0x50c0-0x50df,0x50e0-0x50ff mem 0xc6006000-0xc6006fff,0xc6007000-0xc6007fff
irq 16 at device 8.1 on pci20

MFC after: 2 weeks

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Fix whitespace and normalize some entries.

Correct the definition for Exar XR17V258IV: we must use a config_function
to specify the offset into the PCI memory spare at which each serial port
will find its registers. This was already done for

Correct the definition for Exar XR17V258IV: we must use a config_function
to specify the offset into the PCI memory spare at which each serial port
will find its registers. This was already done for other Exar PCI serial
devices; it was accidentally omitted for this specific device.

Sponsored by: Sandvine Incorporated
MFC after: 1 week

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Add support for Exar XR17V358 8-port serial device to puc(4)

Reviewed by: marius
Sponsored by: Sandvine Inc.
MFC after: 1 week

- Apparently, r186520 was just wrong and the clock of Oxford OX16PCI958 is
neither DEFAULT_RCLK * 2 nor DEFAULT_RCLK * 10 but plain DEFAULT_RCLK
and there's no (open) source indicating otherwise.

- Apparently, r186520 was just wrong and the clock of Oxford OX16PCI958 is
neither DEFAULT_RCLK * 2 nor DEFAULT_RCLK * 10 but plain DEFAULT_RCLK
and there's no (open) source indicating otherwise. This was tested with
an EXSYS EX-41098-2, whose clock is not configurable and identifies as:
puc0@pci0:5:1:0: class=0x070200 card=0x06711415 chip=0x95381415 rev=0x01 hdr=0x00
vendor = 'Oxford Semiconductor Ltd'
class = simple comms
subclass = multiport serial

Note that this exactly matches the card mentioned in PR 129665 so no
sub-device/sub-vendor based quirking of the latter is possible. So maybe
we should grow some sort of tunable, in case non-default cards such as
the latter aren't configurable either (this also wouldn't be the first
time an allegedly tested commit turns out to be wrong though).
- Make the TiMedia tables const.

MFC after: 1 week

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Add support for Advantech PCI-1602 RS-485/RS-422 serial card

PR: kern/169726
Submitted by: Jan Mikkelsen <[email protected]>
Approved by: cperciva (implicit)
MFC after: 5 days

Add support for SIIG Cyber Serial Dual PCI 16C850

Submitted by: David Boyd [email protected]
Approved by: cperciva
MFC after: 3 days

Add additional Perle Speed LE serial cards

PR: kern/168816
Submitted by: Dennis Oyama <[email protected]>
Approved by: cperciva
MFC after: 1 week

- Change back "d_ofs" to int8_t to not pessimize padding and size of "struct puc_cfg".
- Use "puc_config_moxa" for Moxa boards that need d_ofs greater than 0x7f

Prodded by: marcel@, gavin@
MFC after

- Change back "d_ofs" to int8_t to not pessimize padding and size of "struct puc_cfg".
- Use "puc_config_moxa" for Moxa boards that need d_ofs greater than 0x7f

Prodded by: marcel@, gavin@
MFC after: 3 days

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