Lines Matching refs:CSR_WRITE_4
548 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); in msk_miibus_statchg()
632 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_setvlan()
634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_setvlan()
637 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_setvlan()
639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_setvlan()
1254 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in msk_phy_power()
1299 CSR_WRITE_4(sc, B2_GP_IO, val); in msk_phy_power()
1357 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); in mskc_reset()
1366 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); in mskc_reset()
1420 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); in mskc_reset()
1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); in mskc_reset()
1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); in mskc_reset()
1425 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), in mskc_reset()
1435 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); in mskc_reset()
1443 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); in mskc_reset()
1493 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); in mskc_reset()
1495 CSR_WRITE_4(sc, B0_IMSK, 0); in mskc_reset()
1526 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); in mskc_reset()
1527 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); in mskc_reset()
1530 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); in mskc_reset()
1531 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); in mskc_reset()
1549 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); in mskc_reset()
1554 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); in mskc_reset()
1557 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); in mskc_reset()
2073 CSR_WRITE_4(sc, B0_IMSK, 0); in mskc_detach()
2075 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); in mskc_detach()
3018 CSR_WRITE_4(sc, B0_IMSK, 0); in mskc_suspend()
3020 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); in mskc_suspend()
3408 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_intr_gmac()
3412 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_intr_gmac()
3451 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_handle_hwerr()
3457 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); in msk_handle_hwerr()
3462 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); in msk_handle_hwerr()
3534 CSR_WRITE_4(sc, B0_HWE_IMSK, in msk_intr_hwerr()
3688 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); in msk_intr()
3712 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); in msk_intr()
3718 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); in msk_intr()
3726 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); in msk_intr()
3729 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); in msk_intr()
3752 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_set_tx_stfwd()
3757 CSR_WRITE_4(sc, in msk_set_tx_stfwd()
3761 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_set_tx_stfwd()
3764 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_set_tx_stfwd()
3816 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); in msk_init_locked()
3817 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); in msk_init_locked()
3818 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); in msk_init_locked()
3821 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), in msk_init_locked()
3879 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); in msk_init_locked()
3880 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); in msk_init_locked()
3885 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); in msk_init_locked()
3892 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); in msk_init_locked()
3895 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), in msk_init_locked()
3911 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); in msk_init_locked()
3912 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); in msk_init_locked()
3913 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); in msk_init_locked()
3933 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); in msk_init_locked()
3952 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); in msk_init_locked()
3953 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); in msk_init_locked()
3954 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); in msk_init_locked()
3970 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), in msk_init_locked()
3976 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); in msk_init_locked()
3977 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); in msk_init_locked()
3978 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); in msk_init_locked()
3983 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); in msk_init_locked()
3997 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); in msk_init_locked()
4018 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_init_locked()
4031 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); in msk_init_locked()
4034 CSR_WRITE_4(sc, B2_IRQM_INI, in msk_init_locked()
4036 CSR_WRITE_4(sc, B2_IRQM_VAL, in msk_init_locked()
4041 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); in msk_init_locked()
4043 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); in msk_init_locked()
4067 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), in msk_set_rambuffer()
4069 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), in msk_set_rambuffer()
4071 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), in msk_set_rambuffer()
4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), in msk_set_rambuffer()
4082 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); in msk_set_rambuffer()
4083 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); in msk_set_rambuffer()
4091 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), in msk_set_rambuffer()
4093 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), in msk_set_rambuffer()
4095 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), in msk_set_rambuffer()
4097 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), in msk_set_rambuffer()
4111 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), in msk_set_prefetch()
4113 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), in msk_set_prefetch()
4116 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), in msk_set_prefetch()
4118 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), in msk_set_prefetch()
4124 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), in msk_set_prefetch()
4156 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); in msk_stop()
4158 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); in msk_stop()
4171 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); in msk_stop()
4175 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), in msk_stop()
4196 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), in msk_stop()
4200 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), in msk_stop()
4207 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); in msk_stop()
4209 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); in msk_stop()
4232 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), in msk_stop()
4235 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), in msk_stop()
4240 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); in msk_stop()