Lines Matching refs:CSR_WRITE_4
216 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in age_miibus_readreg()
245 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in age_miibus_writereg()
345 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); in age_get_macaddr()
353 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
387 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); in age_phy_reset()
389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); in age_phy_reset()
1317 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); in age_setwol()
1410 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); in age_setwol()
1418 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_setwol()
1873 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_ioctl()
1947 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_mac_config()
1991 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | in age_link_task()
1994 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_link_task()
2111 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); in age_intr()
2185 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); in age_int_task()
2521 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); in age_reset()
2533 CSR_WRITE_4(sc, 0x12FC, 0x6500); in age_reset()
2534 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); in age_reset()
2591 CSR_WRITE_4(sc, AGE_PAR0, in age_init_locked()
2593 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); in age_init_locked()
2597 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); in age_init_locked()
2599 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2601 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2603 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2605 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2607 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); in age_init_locked()
2609 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, in age_init_locked()
2614 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, in age_init_locked()
2618 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); in age_init_locked()
2634 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, in age_init_locked()
2641 CSR_WRITE_4(sc, AGE_HDPX_CFG, in age_init_locked()
2659 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); in age_init_locked()
2672 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); in age_init_locked()
2675 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, in age_init_locked()
2689 CSR_WRITE_4(sc, 0x12FC, 0x6500); in age_init_locked()
2694 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); in age_init_locked()
2730 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, in age_init_locked()
2735 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, in age_init_locked()
2742 CSR_WRITE_4(sc, AGE_RXQ_CFG, in age_init_locked()
2752 CSR_WRITE_4(sc, AGE_TXQ_CFG, in age_init_locked()
2761 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, in age_init_locked()
2767 CSR_WRITE_4(sc, AGE_DMA_CFG, in age_init_locked()
2773 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, in age_init_locked()
2780 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, in age_init_locked()
2784 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); in age_init_locked()
2785 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); in age_init_locked()
2791 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); in age_init_locked()
2800 CSR_WRITE_4(sc, AGE_MAC_CFG, in age_init_locked()
2814 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); in age_init_locked()
2815 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); in age_init_locked()
2818 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); in age_init_locked()
2852 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); in age_stop()
2853 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); in age_stop()
2855 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); in age_stop()
2860 CSR_WRITE_4(sc, AGE_DMA_CFG, in age_stop()
2863 CSR_WRITE_4(sc, AGE_TXQ_CFG, in age_stop()
2865 CSR_WRITE_4(sc, AGE_RXQ_CFG, in age_stop()
2918 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_stop_txmac()
2924 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); in age_stop_txmac()
2947 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_stop_rxmac()
2953 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); in age_stop_rxmac()
3121 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_rxvlan()
3156 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); in age_rxfilter()
3157 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); in age_rxfilter()
3158 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); in age_rxfilter()
3166 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); in age_rxfilter()
3167 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); in age_rxfilter()
3168 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); in age_rxfilter()